Commit b78e9468 authored by Ivo Júnior's avatar Ivo Júnior

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-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- UFPR, BCC, ci210 2015-2 trabalho semestral, autor: Roberto Hexsel, 27out
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ESTE ARQUIVO NAO PODE SER ALTERADO
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- le um arquivo, um inteiro por vez
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity read_data_file is
generic (INPUT_FILE_NAME : string := "input.data");
port (rst, clk : in bit;
data : out bit_vector;
eof : out boolean);
end entity read_data_file;
architecture behavioral of read_data_file is
type uint_file_type is file of integer;
file input_file: uint_file_type open read_mode is INPUT_FILE_NAME;
begin
U_read: process
variable datum : integer := 0;
begin
eof <= FALSE;
while not endfile(input_file) loop
wait until rising_edge(clk);
read( input_file, datum );
-- assert FALSE report "fileRD: " & integer'image( datum ); -- DEBUG
data <= SLV2BV32( std_logic_vector(to_signed(datum,32)) );
end loop;
eof <= TRUE;
wait;
end process U_read;
end behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- escreve um inteiro na saida padrao do simulador
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity write_int is
port (rst, clk : in bit;
sel : in bit; -- active in '1'
data : in reg32);
end write_int;
architecture behavioral of write_int is
file output : text open write_mode is "STD_OUTPUT";
begin
U_write_uint: process(clk, sel)
variable msg : line;
begin
if rising_edge(clk) and sel = '1' then
write ( msg, string'(BV32HEX(data)) );
writeline( output, msg );
end if;
end process U_write_uint;
end behavioral;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- escreve sete inteiros na saida padrao do simulador
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity write_int7 is
port (rst,clk : in bit;
sigma : in integer;
epsilon : in integer;
delta : in integer;
prop : in integer;
integr : in integer;
deriv : in integer;
lambda : in integer);
end write_int7;
architecture behavioral of write_int7 is
file output : text open write_mode is "STD_OUTPUT";
begin
U_write_uint: process(clk)
variable msg : line;
begin
if rising_edge(clk) then
write ( msg, integer'image(sigma));
write ( msg, ' ');
write ( msg, integer'image(epsilon));
write ( msg, ' ');
write ( msg, integer'image(delta));
write ( msg, ' ');
write ( msg, integer'image(prop));
write ( msg, ' ');
write ( msg, integer'image(integr));
write ( msg, ' ');
write ( msg, integer'image(deriv));
write ( msg, ' ');
write ( msg, integer'image(lambda));
writeline( output, msg );
end if;
end process U_write_uint;
end behavioral;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
#include <stdio.h>
#include <stdlib.h>
#define BUF_SZ 64
int buf[BUF_SZ] = {
0,0,
14,14,14,14,14,14,14,
14,16,18,20,22,24,26, // 15
28,28,28,28,28,28,28,28, // 23
0,0,
-17,-17,-17,-17,-17,-17, // 31
-17,-17,-17,-17,-17,-17,-17,-17, // 39
-13,-9,-5,0,
0,0,0,0, // 47
0,0,0,0,
0,0,0,0,
0,0,0,0,
0,0,0,0
};
int main(int argc, char *argv[]) {
int i;
int n;
for (i=0; i<BUF_SZ; i++) {
n = buf[i];
fwrite(&n, sizeof(int), 1, stdout);
}
return(0);
}
File added
0 0 0 0 0 0 0
0 0 1 2 0 0 0
0 0 1 2 2 0 0
14 0 15 30 4 0 5
14 1 16 32 34 28 15
14 4 19 38 66 28 22
14 8 23 46 104 28 29
14 13 28 56 150 28 39
14 19 34 68 206 28 50
14 26 41 82 274 28 64
14 36 51 102 356 28 81
16 48 65 130 458 28 102
18 63 82 164 588 32 130
20 82 103 206 752 36 165
22 105 128 256 958 40 209
24 135 160 320 1214 44 263
26 171 198 396 1534 48 329
28 216 245 490 1930 52 412
28 272 301 602 2420 56 513
28 341 370 740 3022 56 636
28 426 455 910 3762 56 788
28 530 559 1118 4672 56 974
28 657 686 1372 5790 56 1203
28 813 842 1684 7162 56 1483
28 1005 1034 2068 8846 56 1828
0 1243 1244 2488 10914 56 2243
0 1532 1533 3066 13402 0 2744
-17 1882 1866 3732 16468 0 3366
-17 2311 2295 4590 20200 -34 4126
-17 2836 2820 5640 24790 -34 5066
-17 3481 3465 6930 30430 -34 6221
-17 4273 4257 8514 37360 -34 7640
-17 5248 5232 10464 45874 -34 9384
-17 6444 6428 12856 56338 -34 11526
-17 7913 7897 15794 69194 -34 14159
-17 9719 9703 19406 84988 -34 17393
-17 11938 11922 23844 104394 -34 21367
-17 14665 14649 29298 128238 -34 26250
-17 18017 18001 36002 157536 -34 32250
-17 22135 22119 44238 193538 -34 39623
-17 27195 27179 54358 237776 -34 48683
-13 33413 33401 66802 292134 -34 59817
-9 41053 41045 82090 358936 -26 73500
-5 50443 50439 100878 441026 -18 90314
0 61981 61982 123964 541904 -10 110976
0 76159 76160 152320 665868 0 136364
0 93582 93583 187166 818188 0 167559
0 114990 114991 229982 1005354 0 205889
0 141295 141296 282592 1235336 0 252988
0 173619 173620 347240 1517928 0 310861
0 213337 213338 426676 1865168 0 381974
0 262141 262142 524284 2291844 0 469354
0 322109 322110 644220 2816128 0 576724
0 395795 395796 791592 3460348 0 708656
0 486339 486340 972680 4251940 0 870770
0 597595 597596 1195192 5224620 0 1069968
0 734302 734303 1468606 6419812 0 1314736
0 902284 902285 1804570 7888418 0 1615498
0 1108693 1108694 2217388 9692988 0 1985062
0 1362320 1362321 2724642 11910376 0 2439169
0 1673968 1673969 3347938 14635018 0 2997159
0 2056908 2056909 4113818 17982956 0 3682795
0 2527450 2527451 5054902 22096774 0 4525279
0 3105635 3105636 6211272 27151676 0 5560491
File added
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- UFPR, BCC, ci210 2013-1 trabalho semestral, autor: Roberto Hexsel, 01jul
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ESTE ARQUIVO NAO PODE SER ALTERADO
library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all;
library std; use std.textio.all;
package p_WIRES is -- tipos para os barramentos e sinais
constant t_clock_period : time := 1 ns;
constant t_reset : time := 100 ps;
constant simulate_time : integer := 0; -- 1 para simular com tempo != zero
constant t_inv : time := simulate_time*15.0 ps;
constant t_and2 : time := simulate_time*22.0 ps;
constant t_and3 : time := simulate_time*26.6 ps;
constant t_and4 : time := simulate_time*33.2 ps;
constant t_and5 : time := simulate_time*40.0 ps;
constant t_or2 : time := simulate_time*22.0 ps;
constant t_or3 : time := simulate_time*26.6 ps;
constant t_or4 : time := simulate_time*33.2 ps;
constant t_or5 : time := simulate_time*40.0 ps;
constant t_xor2 : time := simulate_time*24.0 ps;
constant t_xor3 : time := simulate_time*29.0 ps;
constant t_rej : time := simulate_time*10.0 ps; -- rejeita pulsos estreitos
constant t_FFD : time := simulate_time*45.0 ps;
constant t_FFT : time := simulate_time*44.0 ps;
subtype reg2 is bit_vector(1 downto 0);
subtype reg3 is bit_vector(2 downto 0);
subtype reg4 is bit_vector(3 downto 0);
subtype reg5 is bit_vector(4 downto 0);
subtype reg8 is bit_vector(7 downto 0);
subtype reg9 is bit_vector(8 downto 0);
subtype reg10 is bit_vector(9 downto 0);
subtype reg12 is bit_vector(11 downto 0);
subtype reg13 is bit_vector(12 downto 0);
subtype reg14 is bit_vector(13 downto 0);
subtype reg15 is bit_vector(14 downto 0);
subtype reg16 is bit_vector(15 downto 0);
subtype reg17 is bit_vector(16 downto 0);
subtype reg20 is bit_vector(19 downto 0);
subtype reg24 is bit_vector(23 downto 0);
subtype reg30 is bit_vector(29 downto 0);
subtype reg31 is bit_vector(30 downto 0);
subtype reg32 is bit_vector(31 downto 0);
subtype reg33 is bit_vector(32 downto 0);
subtype reg63 is bit_vector(62 downto 0);
subtype reg64 is bit_vector(63 downto 0);
subtype reg65 is bit_vector(64 downto 0);
function BIT2INT(i: bit) return integer;
function B2STR(s: in bit) return string;
function BV2STR(s: in bit_vector) return string;
function BV32HEX(w: in bit_vector(31 downto 0)) return string;
function rising_edge(signal s: bit) return boolean;
function falling_edge(signal s: bit) return boolean;
function log2_ceil(n: natural) return natural;
function BV2INT(S: reg32) return integer;
function INT2BV32(S: integer) return reg32;
function INT2BV12(s: integer) return reg12;
function BV2INT12(S: reg12) return integer;
function SLV2BV32(s: std_logic_vector(31 downto 0)) return reg32;
function BV2SLV32(s: reg32) return std_logic_vector;
function SLV2BV8(s: std_logic_vector(7 downto 0)) return reg8;
function BV2SLV8(s: reg8) return std_logic_vector;
end p_WIRES;
package body p_WIRES is
-- ---------------------------------------------------------
function rising_edge(signal S: bit)
return boolean is
begin
if (S'event) and -- ocorreu evento em S
(S = '1') and -- e o valor atual é '1'
(S'last_value = '0') -- e o valor anterior era '0'
then
return TRUE;
else
return FALSE;
end if;
end rising_edge;
-- ---------------------------------------------------------
function falling_edge(signal S: bit)
return boolean is
begin
if (S'event) and -- ocorreu evento em S
(S = '0') and -- e o valor atual é '0'
(S'last_value = '1') -- e o valor anterior era '1'
then
return TRUE;
else
return FALSE;
end if;
end falling_edge;
-- ---------------------------------------------------------
-- find minimum number of bits required to
-- represent N as an unsigned binary number
function log2_ceil(n: natural) return natural is
begin
if n < 2 then
return 0;
else
return 1 + log2_ceil(n/2);
end if;
end log2_ceil;
-- ---------------------------------------------------------
-- convert bit to integer in {0,1}
function BIT2INT(i: bit) return integer is
begin
if i = '1' then
return 1;
else
return 0;
end if;
end BIT2INT;
-- ---------------------------------------------------------
function BV2INT(S: reg32) return integer is
variable result: integer := 0;
begin
if S(31) = '1' then result := -(1024*1024*2); else result := 0; end if;
for i in S'range loop
result := result * 2;
if S(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end BV2INT;
-- ---------------------------------------------------------
function INT2BV32(S: integer) return reg32 is
variable result: reg32;
begin
result := SLV2BV32( std_logic_vector(to_signed(S,32)) );
return result;
end INT2BV32;
-- ---------------------------------------------------------
function BV2INT12(S: reg12) return integer is
variable result: integer;
begin
if S(11) = '1' then result := -4096; else result := 0; end if;
for i in S'range loop
result := result * 2;
if S(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end BV2INT12;
-- ---------------------------------------------------------
function INT2BV12(s: integer) return reg12 is
variable result: reg12;
variable digit: integer := 2**11;
variable local: integer;
begin
local := s;
for i in 11 downto 0 loop
if local/digit >= 1 then
result(i) := '1';
local := local - digit;
else
result(i) := '0';
end if;
digit := digit / 2;
end loop;
return result;
end INT2BV12;
-- ---------------------------------------------------------
function BV2SLV32(s: reg32) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
begin
for i in 31 downto 0 loop
if s(i) = '1' then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
return result;
end BV2SLV32;
-- ---------------------------------------------------------
function SLV2BV32(s: std_logic_vector(31 downto 0)) return reg32 is
variable result: reg32;
begin
for i in 31 downto 0 loop
if s(i) = '1' then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
return result;
end SLV2BV32;
-- ---------------------------------------------------------
function BV2SLV8(s: reg8) return std_logic_vector is
variable result: std_logic_vector(7 downto 0);
begin
for i in 7 downto 0 loop
if s(i) = '1' then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
return result;
end BV2SLV8;
-- ---------------------------------------------------------
function SLV2BV8(s: std_logic_vector(7 downto 0)) return reg8 is
variable result: reg8;
begin
for i in 7 downto 0 loop
if s(i) = '1' then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
return result;
end SLV2BV8;
-- ---------------------------------------------------------
function B2STR(s: in bit) return string is
variable stmp : string(2 downto 1);
begin
if s = '1' then
stmp(1) := '1';
elsif s = '0' then
stmp(1) := '0';
else
stmp(1) := 'x';
end if;
return stmp;
end;
-- ---------------------------------------------------------
function BV2STR(s: in bit_vector) return string is
variable stmp : string(s'left+1 downto 1);
begin
for i in s'reverse_range loop
if s(i) = '1' then
stmp(i+1) := '1';
elsif s(i) = '0' then
stmp(i+1) := '0';
else
stmp(i+1) := 'x';
end if;
end loop; -- i
return stmp;
end;
-- ---------------------------------------------------------
-- convert bit_vector(32) to an hexadecimal string
function BV32HEX(w: in bit_vector(31 downto 0)) return string is
variable nibble: reg4;
variable stmp : string(8 downto 1);
begin
for i in 8 downto 1 loop
nibble := w(((i-1)*4+3) downto ((i-1)*4));
case nibble is
when b"0000" => stmp(i) := '0';
when b"0001" => stmp(i) := '1';
when b"0010" => stmp(i) := '2';
when b"0011" => stmp(i) := '3';
when b"0100" => stmp(i) := '4';
when b"0101" => stmp(i) := '5';
when b"0110" => stmp(i) := '6';
when b"0111" => stmp(i) := '7';
when b"1000" => stmp(i) := '8';
when b"1001" => stmp(i) := '9';
when b"1010" => stmp(i) := 'a';
when b"1011" => stmp(i) := 'b';
when b"1100" => stmp(i) := 'c';
when b"1101" => stmp(i) := 'd';
when b"1110" => stmp(i) := 'e';
when b"1111" => stmp(i) := 'f';
when others => stmp(i) := 'x';
end case;
end loop;
return stmp;
end BV32HEX;
-- ---------------------------------------------------------
end p_WIRES;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
File added
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- UFPR, BCC, ci210 2015-2 trabalho semestral, autor: Roberto Hexsel, 22out
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- controlador proporcional-integral-derivativo
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
library ieee; use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity pid is
port (rst,clk : in bit;
sigma : in reg32;
epsilon : in reg32;
lambda : out reg32);
end pid;
architecture functional of pid is
component write_int7 is
port (rst,clk : in bit;
sigma : in integer;
epsilon : in integer;
delta : in integer;
prop : in integer;
integr : in integer;
deriv : in integer;
lambda : in integer);
end component write_int7;
constant k_prop : reg32 := INT2BV32(2*1); -- 2 bits aa direita da virgula
constant k_integr : reg32 := INT2BV32(2*1); -- multiplicados pelo peso
constant k_deriv : reg32 := INT2BV32(2*1); -- relativo dos componentes
-- "desloca" aa direita 8 casas, peso de 1/3 para cada fator
constant k_contrib : reg32 := INT2BV32(BV2INT(k_prop) + BV2INT(k_integr) + BV2INT(k_deriv));
-- declaracao dos componentes
component adderAdianta32 is
port(inpA, inpB : in reg32;
outC : out reg32;
vem : in bit; -- '0' soma, '1' subtrai
vai : out bit);
end component adderAdianta32;
-- declaracao dos sinais internos
signal i_sigma,i_epsilon,i_delta,i_prop,i_integr,i_deriv,i_lambda: reg32 := INT2BV32(0);
signal vai: bit;
begin -- functional
i_sigma <= sigma;
i_epsilon <= epsilon;
U_delta: adderAdianta32 port map(i_epsilon, i_sigma, i_delta, '1', vai);
i_prop <= INT2BV32(BV2INT(i_delta) * BV2INT(k_prop));
U_int: process(clk, rst)
variable sum: integer;
begin
if rst = '0' then
sum := 0;
elsif rising_edge(clk) then
sum := sum + BV2INT(i_delta) * BV2INT(k_integr);
end if;
i_integr <= INT2BV32(sum);
end process U_int;
U_deriv: process(clk, rst)
variable diff: integer;
begin
if rst = '0' then
diff := 0;
elsif rising_edge(clk) then
diff := BV2INT(i_sigma) * BV2INT(k_deriv);
end if;
i_deriv <= INT2BV32(diff);
end process U_deriv;
-- ameniza o efeito das contribuicoes de P, I, D
i_lambda <= INT2BV32((BV2INT(i_prop) + BV2INT(i_integr) + BV2INT(i_deriv)) / BV2INT(k_contrib));
lambda <= i_lambda;
-- NAO ALTERE ESTA PARTE
-- sinais para depuracao, usados para gerar o grafico
-- estes sinais com valores inteiros devem ser gerados pelo seu modelo,
-- a partir dos bits das saidas dos circuitos
U_write: write_int7 port map (rst, clk,
BV2INT(i_sigma), BV2INT(i_epsilon), BV2INT(i_delta),
BV2INT(i_prop), BV2INT(i_integr), BV2INT(i_deriv), BV2INT(i_lambda));
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ----------------------------------------------------------------------
-- modelo do Urubu
-- ----------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.p_wires.all;
entity urubu is
port (rst,clk : in bit;
lambda : in reg32;
epsilon : out reg32);
end urubu;
architecture functional of urubu is
constant linear_limit : integer := 20;
constant linearity_factor : integer := 0; -- deve ser >= 0
component registerN is
generic (NUM_BITS: integer; INIT_VAL: bit_vector);
port(clk, rst, ld: in bit;
D: in bit_vector;
Q: out bit_vector);
end component registerN;
signal dly_1, dly_2, dly_3, dly_4 : integer := 0;
signal dly_5, dly_6, dly_7, dly_8, i_lambda : integer := 0;
signal val_1, val_2, val_3, val_4 : integer := 0;
signal val_5, val_6, val_7, val_8 : integer := 0;
signal i_linear, i_error : integer := 0;
begin
-- sistema linear, com atraso
i_lambda <= to_integer(signed(to_stdlogicvector(lambda)));
-- simula nao-linearidade
-- altere linear_limit e linearity_factor para experimentar
U_linear: process(i_lambda)
begin
if i_lambda >= 0 then
if i_lambda < linear_limit then
i_linear <= i_lambda;
else
i_linear <= i_lambda + (i_lambda * linearity_factor);
end if;
else -- i_lambda < 0
if i_lambda > (0 - linear_limit) then
i_linear <= i_lambda;
else
i_linear <= i_lambda + (i_lambda * linearity_factor);
end if;
end if;
end process;
-- simula atraso/inercia na resposta do Urubu
U_dly1: process(clk)
begin
if rising_edge(clk) then dly_1 <= i_linear; end if;
end process;
U_dly2: process(clk)
begin
if rising_edge(clk) then dly_2 <= dly_1; end if;
end process;
U_dly3: process(clk)
begin
if rising_edge(clk) then dly_3 <= dly_2; end if;
end process;
U_dly4: process(clk)
begin
if rising_edge(clk) then dly_4 <= dly_3; end if;
end process;
U_dly5: process(clk)