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cMIPS

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cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
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The VHDL model mimics the pipeline design described in Patterson & Hennessy's
book (Computer Organisation and Design) and is an (almost) complete
implementation of the MIPS32r2 instruction set.

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The model was synthesized for an Altera EP4CE30F23.  The model runs at 50 MHz
(top development board speed) and uses up 15% of combinational blocks and
5% of logic registers in the FPGA.
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Processor model runs C code, compiled with GCC;  there are scripts to
compile and assemble code to run on the simulator or the FPGA.
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Core has all forwarding paths and full interlocks for data and control hazards.
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Coprocessor0 is partially implemented, six hardware interrupts + NMI in
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"Interrupt Compatibility Mode";  TLB implementation will be available soon.
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The control instructions break, syscall, trap, mfc0, mtc0, eret, ei, di, ll, sc
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are fully implemented.
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Partial-word loads and stores (word, half-word, byte) implemented at the
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processor's memory interface.
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Testbench for tests includes processor, RAM, ROM and (simulator) file I/O.
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Top level file for synthesis includes processor, RAM, ROM, LCD display,
2x7segment LED display, keypad and UART.  TLB, SDRAM controller, VGA interface
are in the works.