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The repository was moved to https://github.com/rhexsel/cmips
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This repo will not be updated.

28th april 2017.






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cMIPS

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cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
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The VHDL model mimics the pipeline design described in Patterson & Hennessy's
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book (Computer Organisation and Design) and is a complete implementation
of the MIPS32r2 instruction set.
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The model was synthesized for an Altera EP4CE30F23.  The model runs at 50 MHz
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(top board speed) and uses up 22% of the combinational blocks, 9% of the
logic registers, and 33% of the memory bits on the FPGA.
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The processor model runs C code, compiled with GCC;  there are scripts to
compile and assemble code to run on the simulator or for sythesis.
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The core has all forwarding paths and is fully interlocked for data and
control hazards.
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Coprocessor0 supports six hardware interrupts + NMI in "Interrupt
Compatibility Mode" and an 8-way fully associative TLB.  The control
instructions break, syscall, trap, mfc0, mtc0, eret, ei, di, ll, sc
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are fully implemented.
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Partial-word loads and stores (word, half-word, byte, lwl,lwr,swl,swr) are
implemented.
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A simulation testbench includes processor, RAM, ROM and (simulator) file I/O.
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Top level file for synthesis includes processor, RAM, ROM, LCD display
controller, 2x7segment LED display, keypad and UART.  SDRAM controller,
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VGA interface and Ethernet port are in the works.

See docs/cMIPS.pdf for a more complete description.