Commit 2c424a99 authored by Roberto Hexsel's avatar Roberto Hexsel

SDRAM controller's state machine written

parent eea4da3a
Pipeline #1774 skipped
......@@ -66,7 +66,7 @@ simulator=tb_cmips
pkg="packageWires.vhd packageMemory.vhd packageExcp.vhd"
src="aux.vhd altera.vhd macnica.vhd memory.vhd cache.vhd instrcache.vhd ram.vhd rom.vhd units.vhd io.vhd uart.vhd fpu.vhd pipestages.vhd exception.vhd core.vhd tb_cMIPS.vhd"
src="aux.vhd altera.vhd macnica.vhd memory.vhd cache.vhd instrcache.vhd sdram.vhd ram.vhd rom.vhd units.vhd io.vhd uart.vhd fpu.vhd pipestages.vhd exception.vhd core.vhd tb_cMIPS.vhd"
# build simulator
#ghdl --clean
......
This diff is collapsed.
......@@ -287,6 +287,29 @@ architecture TB of tb_cMIPS is
dump_ram : in std_logic);
end component fpga_RAM;
component SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk2x : in std_logic; -- 100MHz clock
hcs : in std_logic; -- host side chip select (=0)
rdy : in std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
component fake_I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
......@@ -477,6 +500,27 @@ architecture TB of tb_cMIPS is
signal LCD_DATA : std_logic_vector(7 downto 0); -- LCD data bus
signal LCD_RS, LCD_RW, LCD_EN, LCD_BLON : std_logic; -- LCD control
signal uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq : std_logic;
signal hcs : std_logic; -- host side chip select (=0)
signal sdram_rdy : std_logic; -- host side chip select (=0)
signal haddr : reg26; -- host side address
signal hDinp : reg32; -- host side data input
signal hDout : reg32; -- host side data output
signal sdcke : std_logic; -- ram side clock enable
signal sdscs : std_logic; -- ram side chip select
signal sdras : std_logic; -- ram side RAS
signal sdcas : std_logic; -- ram side CAS
signal sdwe : std_logic; -- ram side write enable
signal sddqm0 : std_logic; -- ram side byte0 output enable
signal sddqm1 : std_logic; -- ram side byte0 output enable
signal sdba0 : std_logic; -- ram side bank select 0
signal sdba1 : std_logic; -- ram side bank select 1
signal sdaddr : reg12; -- ram side address
signal sddata : reg16; -- ram side data
begin -- TB
......@@ -587,6 +631,10 @@ begin -- TB
mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
U_SDRAM_controller : SDRAM_controller port map
(rst, clk,hcs,sdram_rdy,wr,cpu_xfer,haddr,hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
U_to_stdout: to_stdout
port map (rst,clk, io_stdout_sel, wr, cpu_data);
......
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