Commit 3ef8ae5e authored by Roberto Hexsel's avatar Roberto Hexsel

edit to README

parent 981cbff7
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's
book (Computer Organisation and Design) and is an (almost) complete
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