Commit 64d9cccb authored by Roberto Hexsel's avatar Roberto Hexsel

added fake_SDRAM_controller

parent 2c424a99
Pipeline #2140 skipped
......@@ -49,6 +49,7 @@ package p_WIRES is
subtype reg9 is std_logic_vector(8 downto 0);
subtype reg10 is std_logic_vector(9 downto 0);
subtype reg12 is std_logic_vector(11 downto 0);
subtype reg13 is std_logic_vector(12 downto 0);
subtype reg16 is std_logic_vector(15 downto 0);
subtype reg17 is std_logic_vector(16 downto 0);
subtype reg18 is std_logic_vector(17 downto 0);
......@@ -57,6 +58,7 @@ package p_WIRES is
subtype reg21 is std_logic_vector(20 downto 0);
subtype reg23 is std_logic_vector(22 downto 0);
subtype reg24 is std_logic_vector(23 downto 0);
subtype reg26 is std_logic_vector(25 downto 0);
subtype reg28 is std_logic_vector(27 downto 0);
subtype reg30 is std_logic_vector(29 downto 0);
subtype reg31 is std_logic_vector(30 downto 0);
......
......@@ -37,7 +37,7 @@ entity SDRAM_controller is
clk2x : in std_logic; -- 100MHz clock
hcs : in std_logic; -- host side chip select (=0)
rdy : in std_logic; -- tell CPU to wait (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
......@@ -430,3 +430,59 @@ begin -- simple
end simple;
-- ---------------------------------------------------------------------
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- fake SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity fake_SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk2x : in std_logic; -- 100MHz clock
hcs : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end entity fake_SDRAM_controller;
architecture fake of fake_SDRAM_controller is
begin
rdy <= '1';
hDout <= (others => 'X');
cke <= '1';
scs <= '1';
ras <= '1';
cas <= '1';
we <= '1';
dqm0 <= '1';
dqm1 <= '1';
ba0 <= '1';
ba1 <= '1';
saddr <= (others => 'X');
sdata <= (others => 'X');
end architecture fake;
......@@ -291,7 +291,7 @@ architecture TB of tb_cMIPS is
port (rst : in std_logic; -- FPGA reset (=0)
clk2x : in std_logic; -- 100MHz clock
hcs : in std_logic; -- host side chip select (=0)
rdy : in std_logic; -- tell CPU to wait (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
......@@ -310,6 +310,29 @@ architecture TB of tb_cMIPS is
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
component fake_SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk2x : in std_logic; -- 100MHz clock
hcs : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end component fake_SDRAM_controller;
component fake_I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
......@@ -502,22 +525,22 @@ architecture TB of tb_cMIPS is
signal uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq : std_logic;
signal hcs : std_logic; -- host side chip select (=0)
signal hcs : std_logic; -- host side chip select (=0)
signal sdram_rdy : std_logic; -- host side chip select (=0)
signal haddr : reg26; -- host side address
signal hDinp : reg32; -- host side data input
signal hDout : reg32; -- host side data output
signal sdcke : std_logic; -- ram side clock enable
signal sdscs : std_logic; -- ram side chip select
signal sdras : std_logic; -- ram side RAS
signal sdcas : std_logic; -- ram side CAS
signal sdwe : std_logic; -- ram side write enable
signal sddqm0 : std_logic; -- ram side byte0 output enable
signal sddqm1 : std_logic; -- ram side byte0 output enable
signal sdba0 : std_logic; -- ram side bank select 0
signal sdba1 : std_logic; -- ram side bank select 1
signal sdaddr : reg12; -- ram side address
signal sddata : reg16; -- ram side data
signal haddr : reg26; -- host side address
signal hDinp : reg32; -- host side data input
signal hDout : reg32; -- host side data output
signal sdcke : std_logic; -- ram side clock enable
signal sdscs : std_logic; -- ram side chip select
signal sdras : std_logic; -- ram side RAS
signal sdcas : std_logic; -- ram side CAS
signal sdwe : std_logic; -- ram side write enable
signal sddqm0 : std_logic; -- ram side byte0 output enable
signal sddqm1 : std_logic; -- ram side byte0 output enable
signal sdba0 : std_logic; -- ram side bank select 0
signal sdba1 : std_logic; -- ram side bank select 1
signal sdaddr : reg12; -- ram side address
signal sddata : reg16; -- ram side data
......@@ -630,11 +653,11 @@ begin -- TB
port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
U_SDRAM_controller : SDRAM_controller port map
-- U_SDRAM_controller : SDRAM_controller port map
U_SDRAM_controller : fake_SDRAM_controller port map
(rst, clk,hcs,sdram_rdy,wr,cpu_xfer,haddr,hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
U_to_stdout: to_stdout
port map (rst,clk, io_stdout_sel, wr, cpu_data);
......
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