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Commit 791396a2 authored by Roberto Hexsel's avatar Roberto Hexsel
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page table walk, several fixes

parent e21ec516
Pipeline #4069 skipped
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cMIPS/bin/assemble.sh
View file @ 791396a2
......@@ -32,6 +32,7 @@ OPTIONS:
-h Show this message
-O n Optimization level, defaults to n=0 {0,1,2,3}
-v Verbose, creates memory map: SOURCE.map
-n when verbose, display register names instead of numbers
-mif Generate output file ROM.mif for Altera's FPGAs
EOF
}
......@@ -54,6 +55,7 @@ if [ $# = 0 ] ; then usage ; exit 1 ; fi
miffile=false
verbose=false
names=false
unset mem_map
level=0
......@@ -82,6 +84,8 @@ while true ; do
;;
-v) verbose=true
;;
-n) names=true
;;
-mif|-m) miffile=true
;;
-x) set -x
......@@ -105,6 +109,12 @@ fi
if [ $verbose = true ] ; then mem_map="-Map ${inp}.map" ; fi
if [ $names = true ] ; then
reg_names="-M reg-names=mips2r2 -M cp0-names=mips2r2"
else
reg_names="-M reg-names=numeric -M cp0-names=numeric"
fi
asm=${inp}.s
obj=${inp}.o
elf=${inp}.elf
......@@ -114,18 +124,15 @@ dat=data.bin
(mips-as -O${level} -EL -mips32r2 -I "${include}" -o $obj $asm || exit 1) &&\
mips-ld -EL ${mem_map} -I "${include}" --script $c_ld -o $elf $obj &&\
mips-objcopy -S -j .text -O binary $elf $bin &&\
mips-objcopy -S -j .data -j .rodata -O binary $elf $dat &&\
mips-objcopy -S -j .data -j .rodata -j .PT -O binary $elf $dat &&\
chmod a-x $bin $dat &&\
if [ $verbose = true ] ; then
mips-objdump -z -D -EL -M reg-names=numeric -M cp0-names=mips2r2 \
--show-raw-insn \
mips-objdump -z -D -EL $reg_names --show-raw-insn \
--section .text --section .data --section .rodata --section .bss $elf
fi &&\
if [ $miffile = true ] ; then
elf2mif.sh "$elf" || exit 1
fi
# -M reg-names=mips2r2 -M cp0-names=mips2r2 reg-names=numeric \
# --section .reginfo
cMIPS/bin/compile.sh
View file @ 791396a2
......@@ -33,6 +33,7 @@ OPTIONS:
-h Show this message
-O n Optimization level, defaults to n=1 {0,1,2,3}
-v Verbose, creates memory map: source.map
-n when verbose, display register numbers instead of names
-W Pass -Wall on to GCC
-mif Generate output file ROM.mif for Altera's FPGAs
-syn Compile for synthesis, else for simulation
......@@ -57,6 +58,7 @@ if [ $# = 0 ] ; then usage ; exit 1 ; fi
miffile=false
synth=false
verbose=false
names=true
unset memory_map
level=1
......@@ -80,6 +82,8 @@ while true ; do
;;
-v) verbose=true
;;
-n) names=false
;;
-mif) miffile=true
;;
-syn) synth=true
......@@ -146,15 +150,20 @@ mips-ld -EL -e _start ${memory_map} -I "${include}" --script $c_ld \
mips-objcopy -S -j .text -O binary $elf $bin && \
mips-objcopy -S -j .data -j .rodata -j .rodata1 -j .data1 \
-j .sdata -j .lit8 -j .lit4 -j .sbss -j .bss \
-j .sdata -j .lit8 -j .lit4 -j .sbss -j .bss -j .PT \
-O binary $elf $dat || exit 1
if [ $names = true ] ; then
reg_names="-M reg-names=mips2r2 -M cp0-names=mips2r2"
else
reg_names="-M reg-names=numeric -M cp0-names=numeric"
fi
if [ $? == 0 -a $verbose = true ]; then
mips-objdump -z -D -EL -M reg-names=mips2r2 -M cp0-names=mips2r2 \
--show-raw-insn \
mips-objdump -z -D -EL $reg_names --show-raw-insn \
--section .text --section .data \
--section .rodata --section .sdata --section .sbss \
--section .bss $elf
--section .bss --section .PT $elf
fi
if [ $? == 0 -a $miffile = true ] ; then
......
cMIPS/docs/cMIPS.pdf
View file @ 791396a2
No preview for this file type
cMIPS/include/cMIPS.h
View file @ 791396a2
#define x_INST_BASE_ADDR 0x00000000
#define x_DATA_BASE_ADDR 0x00010000
#define x_DATA_BASE_ADDR 0x00040000
#define x_DATA_MEM_SZ 0x00020000
#define x_SDRAM_BASE_ADDR 0x04000000
#define x_SDRAM_MEM_SZ 0x02000000
#define x_IO_BASE_ADDR 0x3c000000
......
cMIPS/include/cMIPS.ld
View file @ 791396a2
......@@ -5,8 +5,8 @@ MEMORY
{
rom (rx) : ORIGIN = 0x00000000, /* x_INST_BASE_ADDR */
LENGTH = 0x00004000, /* x_INST_MEM_SZ */
ram (!rx) : ORIGIN = 0x00010000, /* x_DATA_BASE_ADDR */
LENGTH = 0x00008000, /* x_DATA_MEM_SZ */
ram (!rx) : ORIGIN = 0x00040000, /* x_DATA_BASE_ADDR */
LENGTH = 0x00020000, /* x_DATA_MEM_SZ */
sdram (!rx) : ORIGIN = 0x04000000, /* x_SDRAM_BASE_ADDR */
LENGTH = 0x02000000, /* x_SDRAM_MEM_SZ */
io (!rx) : ORIGIN = 0x3c000000, /* not used, do not remove */
......@@ -40,8 +40,9 @@ SECTIONS
_end = . ; /* end of image constant (from Xinu) */
} > ram
end_RAM = 0x00008000; /* x_DATA_MEM_SZ */
end_RAM = 0x00020000; /* x_DATA_MEM_SZ */
half_RAM = (end_RAM / 2);
base_TP = ( _bdata + half_RAM );
.TP base_TP : { *(.TP) } > ram
base_PT = ( _bdata + half_RAM );
.PT base_PT : { *(.PT) } > ram
}
cMIPS/include/cMIPS.s
View file @ 791396a2
......@@ -3,8 +3,8 @@
.set x_INST_BASE_ADDR,0x00000000
.set x_INST_MEM_SZ,0x00004000
.set x_DATA_BASE_ADDR,0x00010000
.set x_DATA_MEM_SZ,0x00008000
.set x_DATA_BASE_ADDR,0x00040000
.set x_DATA_MEM_SZ,0x00020000
.set x_IO_BASE_ADDR,0x3c000000
.set x_IO_MEM_SZ,0x00002000
......@@ -71,8 +71,9 @@
# reset: COP0 present, at exception level, all else disabled
.set cop0_STATUS_reset,0x10000002
.set c0_status_reset, cop0_STATUS_reset
# normal state: COP0 present, user mode, all IRQs enabled
.set cop0_STATUS_normal,0x1000ff11
# reset: COUNTER stopped, use special interrVector, no interrupts
.set cop0_CAUSE_reset, 0x0880007c
.set c0_cause_reset, cop0_CAUSE_reset
cMIPS/include/cMIPSio.c
View file @ 791396a2
......@@ -348,10 +348,10 @@ void DSP7SEGput(int MSD, int MSdot, int lsd, int lsdot) {
//=======================================================================
// external counter -- counts down to zero and stops or interrupts
// external counter -- counts up to limit, then stops or interrupts
//=======================================================================
// write an integer with number of pulses to count and start counter
// if interr is not 0, then will interrupt when count reaches zero
// if interr is not 0, then raise an interrupt when count reaches 'n'
void startCounter(int n, int interr) {
int *IO = (int *)IO_COUNT_ADDR;
int interrupt;
......
cMIPS/include/handlers.s
View file @ 791396a2
......@@ -4,7 +4,7 @@
.set noreorder
.align 2
.set M_StatusIEn,0x0000ff09 # STATUS.intEn=1, user mode
.set M_StatusIEn,0x0000ff11 # STATUS.intEn=1, user mode
#----------------------------------------------------------------
# interrupt handler for external counter attached to IP5=HW3
......@@ -57,11 +57,11 @@ extCounter:
# lw $a1, 1*4($k1)
#----------------------------------
mfc0 $k0, cop0_STATUS # Read STATUS register
mfc0 $k0, c0_status # Read STATUS register
ori $k0, $k0, M_StatusIEn # but do not modify its contents
addiu $k1, $zero, -7 # except for re-enabling interrupts
and $k0, $k1, $k0 # -7 = 0xffff.fff9
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
eret # Return from interrupt
.end extCounter
#----------------------------------------------------------------
......@@ -102,10 +102,10 @@ UARTinterr:
lui $k0, %hi(_uart_buff)
ori $k0, $k0, %lo(_uart_buff)
sw $k1, 0($k0) # and save UART status to memory
sw $k1, 0*4($k0) # and save UART status to memory
sw $a0, 12($k0) # save registers $a0,$a1, others?
sw $a1, 16($k0)
sw $a0, 5*4($k0) # save registers $a0,$a1, others?
sw $a1, 6*4($k0)
#----------------------------------
# while you are developing the complete handler,
......@@ -115,7 +115,7 @@ UARTinterr:
andi $a0, $k1, UART_rx_irq # Is this reception?
beq $a0, $zero, UARTret # no, ignore it and return
lui $a0, %hi(HW_uart_addr)
ori $a0, $a0, %lo(HW_uart_addr)
lw $a1, 4($a0) # Read data
......@@ -125,14 +125,14 @@ UARTinterr:
sw $a1, 8($k0) # Signal new arrival
UARTret:
lw $a1, 16($k0) # restore registers $a0,$a1, others?
lw $a0, 12($k0)
lw $a1, 6*4($k0) # restore registers $a0,$a1, others?
lw $a0, 5*4($k0)
mfc0 $k0, cop0_STATUS # Read STATUS register
mfc0 $k0, c0_status # Read STATUS register
ori $k0, $k0, M_StatusIEn # but do not modify its contents
addiu $k1, $zero, -7 # except for re-enabling interrupts
and $k0, $k1, $k0 # -7 = 0xffff.fff9 = user mode
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
eret # Return from interrupt
.end UARTinterr
#----------------------------------------------------------------
......@@ -145,16 +145,16 @@ UARTret:
.global countCompare
.ent countCompare
countCompare:
mfc0 $k1,cop0_COUNT # read COMPARE and clear IRQ
mfc0 $k1,c0_count # read COMPARE and clear IRQ
addiu $k1,$k1,64 # set next interrupt in 64 ticks
mtc0 $k1,cop0_COMPARE
mtc0 $k1,c0_compare
mfc0 $k0, cop0_STATUS # Read STATUS register
mfc0 $k0, c0_status # Read STATUS register
ori $k0, $k0, M_StatusIEn # but do not modify its contents
lui $k1, 0xffff # except for re-enabling interrupts
ori $k1, $k1, 0xfff9 # and going into user mode
and $k0, $k1, $k0
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
eret # Return from interrupt
.end countCompare
#----------------------------------------------------------------
......
cMIPS/include/start.s
View file @ 791396a2
......@@ -21,67 +21,113 @@ _start:
# needed so simulations without a page table will not break
# read TLB[4] and write it to TLB[2]
li $k0, 4
mtc0 $k0, cop0_Index
mtc0 $k0, c0_index
ehb
tlbr
li $k1, 2
mtc0 $k1, cop0_Index
mtc0 $k1, c0_index
ehb
tlbwi
#### this is not needed when simulating with a PageTable
#
# # then set another mapping onto TLB[4] to avoid replicated entries
# li $a0, ( (x_DATA_BASE_ADDR + 8*4096) >>13 )<<13
# mtc0 $a0, c0_entryhi # tag for RAM[8,9] double-page
#
# li $a0, ((x_DATA_BASE_ADDR + 8*4096) >>12)<<6 # RAM[8] (even)
# ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
# mtc0 $a1, c0_entrylo0
#
# li $a0, ((x_DATA_BASE_ADDR + 9*4096) >>12)<<6 # RAM[9] (odd)
# ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
# mtc0 $a1, c0_entrylo1
#
# # and write it to TLB[4]
# li $k0, 4
# mtc0 $k0, c0_index
# tlbwi
####
#
# the page table is located at the middle of the RAM
# bottom half is reserved for "RAM memory", top for page table
#
.set TOP_OF_RAM, (x_DATA_BASE_ADDR + x_DATA_MEM_SZ)
.set MIDDLE_RAM, (x_DATA_BASE_ADDR + (x_DATA_MEM_SZ/2))
# then set another mapping onto TLB[4], to avoid replicated entries
li $a0, ( (x_DATA_BASE_ADDR + 8*4096) >>12 )
sll $a2, $a0, 12 # tag for RAM[8,9] double-page
mtc0 $a2, cop0_EntryHi
# get physical page number for two pages at the top of RAM, for stack
la $a0, ( (MIDDLE_RAM - 2*4096) >>13 )<<13
mtc0 $a0, c0_entryhi # tag for top double-page
li $a0, ((x_DATA_BASE_ADDR + 8*4096) >>12 )
sll $a1, $a0, 6 # RAM[8] (even)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo0
la $a0, ( (MIDDLE_RAM - 2*4096) >>12 )<<6
ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, c0_entrylo0 # top page - 2 (even)
li $a0, ( (x_DATA_BASE_ADDR + 9*4096) >>12 )
sll $a1, $a0, 6 # RAM[9] (odd)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo1
la $a0, ( (MIDDLE_RAM - 1*4096) >>12 )<<6
ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, c0_entrylo1 # top page - 1 (odd)
# and write it to TLB[4]
li $k0, 4
mtc0 $k0, cop0_Index
# and write it to TLB[3]
li $k0, 3
mtc0 $k0, c0_index
tlbwi
# get physical page number for two pages at the top of RAM, for stack
li $a0, ( (x_DATA_BASE_ADDR+x_DATA_MEM_SZ - 2*4096) >>12 )
sll $a2, $a0, 12 # tag for top double-page
mtc0 $a2, cop0_EntryHi
# then set another mapping onto TLB[7], to avoid replicated entries
li $a0, ( (x_DATA_BASE_ADDR + 10*4096) >>13 )<<13
mtc0 $a0, c0_entryhi # tag for RAM[10,11] double-page
li $a0, ( (x_DATA_BASE_ADDR+x_DATA_MEM_SZ - 2*4096) >>12 )
sll $a1, $a0, 6 # top page - 2 (even)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo0
li $a0, ((x_DATA_BASE_ADDR + 10*4096) >>12)<<6 # RAM[10] (even)
ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, c0_entrylo0
li $a0, ( (x_DATA_BASE_ADDR+x_DATA_MEM_SZ - 1*4096) >>12 )
sll $a1, $a0, 6 # top page - 1 (odd)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo1
li $a0, ((x_DATA_BASE_ADDR + 11*4096) >>12)<<6 # RAM[11] (odd)
ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, c0_entrylo1
# and write it to TLB[3]
li $k0, 3
mtc0 $k0, cop0_Index
# and write it to TLB[7]
li $k0, 7
mtc0 $k0, c0_index
tlbwi
# get physical page number for two pages at the bottom of PageTable
la $a0, ( MIDDLE_RAM >>13 )<<13
mtc0 $a0, c0_entryhi # tag for bottom double-page
la $a0, ( (MIDDLE_RAM + 0*4096) >>12 )<<6
ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, c0_entrylo0 # bottom page (even)
la $a0, ( (MIDDLE_RAM + 1*4096) >>12 )<<6
ori $a1, $a0, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, c0_entrylo1 # bottom page + 1 (odd)
# and write it to TLB[4]
li $k0, 4
mtc0 $k0, c0_index
tlbwi
# pin down first four TLB entries: ROM[0], RAM[0], stack and I/O
li $k0, 4
mtc0 $k0, cop0_Wired
# pin down first five TLB entries: ROM[0], I/O, RAM[0], stack, PgTbl
li $k0, 5
mtc0 $k0, c0_wired
# write PageTable base address to Context
la $k0, MIDDLE_RAM
mtc0 $k0, c0_context
# initialize SP at top of RAM: ramTop - 16
li $sp, ((x_DATA_BASE_ADDR+x_DATA_MEM_SZ) - 16)
# set STATUS, cop0, hw interrupt IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, 0x1000e011
mtc0 $k0, cop0_STATUS
# initialize SP at top of usable RAM: (middle of ram) - 16
la $sp, (MIDDLE_RAM - 16)
# set STATUS, cop0, hw interrupts IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, cop0_STATUS_normal
mtc0 $k0, c0_status
jal main # on returning from main(), MUST go into exit()
nop # to stop the simulation.
exit:
......@@ -108,11 +154,11 @@ _excp_0000:
.set noreorder
.set noat
mfc0 $k1, cop0_Context
lw $k0, 0($k1) # k0 <- TP[Context.lo]
lw $k1, 8($k1) # k1 <- TP[Context.hi]
mtc0 $k0, cop0_EntryLo0 # EntryLo0 <- k0 = even element
mtc0 $k1, cop0_EntryLo1 # EntryLo1 <- k1 = odd element
mfc0 $k1, c0_context
lw $k0, 0($k1) # k0 <- TP[context.lo]
lw $k1, 8($k1) # k1 <- TP[context.hi]
mtc0 $k0, c0_entrylo0 # EntryLo0 <- k0 = even element
mtc0 $k1, c0_entrylo1 # EntryLo1 <- k1 = odd element
ehb
tlbwr # update TLB
eret
......@@ -131,8 +177,8 @@ _excp_0100:
.set noat
la $k0, x_IO_BASE_ADDR # PANIC: SHOULD NEVER GET HERE
mfc0 $k1, cop0_CAUSE
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and kill simulation
nop
nop
nop
......@@ -158,11 +204,11 @@ _excp_0100:
.org x_EXCEPTION_0180,0 # exception vector_180
.ent _excp_0180
_excp_0180:
mfc0 $k0, cop0_STATUS
mfc0 $k0, c0_status
lui $k1, %hi(_excp_saves)
ori $k1, $k1, %lo(_excp_saves)
sw $k0, 1*4($k1)
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
sw $k0, 0*4($k1)
andi $k0, $k0, 0x3f # keep only the first 16 ExceptionCodes & b"00"
......@@ -174,7 +220,7 @@ _excp_0180:
nop
excp_tbl: # see Table 8-25, pg 95,96
wait 0x02 # interrupt, should never arrive here, abort simulation
wait 0x02 # interrupt, should never get here, abort simulation
nop
j h_Mod # 1
......@@ -219,7 +265,7 @@ excp_tbl: # see Table 8-25, pg 95,96
wait 0x0f # FP exception, should never get here -- abort simulation
nop
h_Mod:
h_TLBL:
h_TLBS:
......@@ -233,13 +279,12 @@ excp_0180ret:
lui $k1, %hi(_excp_saves) # Read previous contents of STATUS
ori $k1, $k1, %lo(_excp_saves)
lw $k0, 1*4($k1)
# mfc0 $k0, cop0_STATUS
lui $k1, 0xffff # and do not modify its contents
ori $k1, $k1, 0xfff1 # except for re-enabling interrupts
# mfc0 $k0, c0_status
# and do not modify its contents
addi $k1, $zero, -15 # except for re-enabling interrupts
ori $k0, $k0, M_StatusIEn # and keeping user/kernel mode
and $k0, $k1, $k0 # as it was on exception entry
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status # -15 = 0xffff.fff1
eret # Return from exception
.end _excp_0180
......@@ -255,7 +300,7 @@ excp_0180ret:
.extern extCounter # IRQ5 - hwIRQ3, see vhdl/tb_cMIPS.vhd
.set M_CauseIM,0x0000ff00 # keep bits 15..8 -> IM = IP
.set M_StatusIEn,0x0000ff01 # user mode, enable all interrupts
.set M_StatusIEn,0xff11 # user mode, enable all interrupts
.set noreorder
......@@ -263,9 +308,9 @@ excp_0180ret:
.ent _excp_0200
excp_0200:
_excp_0200:
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
andi $k0, $k0, M_CauseIM # Keep only IP bits from Cause
mfc0 $k1, cop0_STATUS
mfc0 $k1, c0_status
and $k0, $k0, $k1 # and mask with IM bits
srl $k0, $k0, 10 # keep only 3 MS bits of IP (irq7..5)
......@@ -304,11 +349,11 @@ dismiss: # No pending request, must have been noise
# do nothing and return
excp_0200ret:
mfc0 $k0, cop0_STATUS # Read STATUS register
mfc0 $k0, c0_status # Read STATUS register
addi $k1, $zero, -15 # and do not modify its contents -15=fff1
ori $k0, $k0, M_StatusIEn # except for re-enabling interrupts
and $k0, $k1, $k0 # and keeping user/kernel mode
mtc0 $k0, cop0_STATUS # as it was on interrupt entry
mtc0 $k0, c0_status # as it was on interrupt entry
eret # Return from interrupt
nop
......@@ -327,7 +372,7 @@ _excp_BFC0:
.set noat
la $k0, x_IO_BASE_ADDR # PANIC: SHOULD NEVER GET HERE
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -342,16 +387,133 @@ _excp_BFC0:
##===============================================================
## main(), normal code starts below -- do not edit next line
.org x_ENTRY_POINT,0
##---------------------------------------------------------------
##
##===============================================================
## reserve first two pages for the Page Table
## Page Table
##
## See EntryLo, pg 63
##
.section .PT,"aw",@progbits
## ( ( (x_INST_BASE_ADDR + n*4096) >>12 )<<6 ) || 0b000011 d,v,g
_PT:
##
## ROM mappings
##
.section .TP,"aw",@progbits
_TP: .skip (2*4096), 0
_endTP:
.org (_PT + (x_INST_BASE_ADDR >>13)*16)
# PT[0], ROM
.word ( (x_INST_BASE_ADDR + 0*4096) >>6) | 0b000011
.word 0
.word ( (x_INST_BASE_ADDR + 1*4096) >>6) | 0b000011
.word 0
# PT[1]
.word ( (x_INST_BASE_ADDR + 2*4096) >>6) | 0b000011
.word 0
.word ( (x_INST_BASE_ADDR + 3*4096) >>6) | 0b000011
.word 0
# PT[2]
.word ( (x_INST_BASE_ADDR + 4*4096) >>6) | 0b000011
.word 0
.word ( (x_INST_BASE_ADDR + 5*4096) >>6) | 0b000011
.word 0
# PT[3]
.word ( (x_INST_BASE_ADDR + 6*4096) >>6) | 0b000011
.word 0
.word ( (x_INST_BASE_ADDR + 7*4096) >>6) | 0b000011
.word 0
# PT[4] -- not mapped for simulation
.word ( (x_INST_BASE_ADDR + 8*4096) >>6) | 0b000001
.word 0
.word ( (x_INST_BASE_ADDR + 9*4096) >>6) | 0b000001
.word 0
# PT[5] -- not mapped for simulation
.word ( (x_INST_BASE_ADDR + 10*4096) >>6) | 0b000001
.word 0
.word ( (x_INST_BASE_ADDR + 11*4096) >>6) | 0b000001
.word 0
# PT[6] -- not mapped for simulation
.word ( (x_INST_BASE_ADDR + 12*4096) >>6) | 0b000001
.word 0
.word ( (x_INST_BASE_ADDR + 13*4096) >>6) | 0b000001
.word 0
# PT[7] -- not mapped for simulation