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Roberto Hexsel
cMIPS
Commits
8cb5a972
Commit
8cb5a972
authored
Apr 07, 2016
by
Roberto Hexsel
Browse files
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Email Patches
Plain Diff
removed all fake entities
parent
64d9cccb
Pipeline
#2141
skipped
Changes
10
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10 changed files
with
423 additions
and
798 deletions
+423
-798
cMIPS/vhdl/altera.vhd
cMIPS/vhdl/altera.vhd
+23
-0
cMIPS/vhdl/cache.vhd
cMIPS/vhdl/cache.vhd
+4
-51
cMIPS/vhdl/fpu.vhd
cMIPS/vhdl/fpu.vhd
+12
-21
cMIPS/vhdl/macnica.vhd
cMIPS/vhdl/macnica.vhd
+22
-0
cMIPS/vhdl/memory.vhd
cMIPS/vhdl/memory.vhd
+0
-330
cMIPS/vhdl/packageMemory.vhd
cMIPS/vhdl/packageMemory.vhd
+3
-0
cMIPS/vhdl/ram.vhd
cMIPS/vhdl/ram.vhd
+189
-3
cMIPS/vhdl/rom.vhd
cMIPS/vhdl/rom.vhd
+121
-271
cMIPS/vhdl/sdram.vhd
cMIPS/vhdl/sdram.vhd
+2
-30
cMIPS/vhdl/tb_cMIPS.vhd
cMIPS/vhdl/tb_cMIPS.vhd
+47
-92
No files found.
cMIPS/vhdl/altera.vhd
View file @
8cb5a972
...
...
@@ -174,6 +174,29 @@ end architecture rtl;
-- -----------------------------------------------------------------------
-- fake ROM megafunction = not used in simulation, only on the FPGA ------
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
IEEE
.
numeric_std
.
all
;
use
work
.
p_wires
.
all
;
use
work
.
p_memory
.
all
;
entity
alt_mf_rom
is
port
(
address
:
IN
STD_LOGIC_VECTOR
((
INST_ADDRS_BITS
-1
)
DOWNTO
0
);
clken
:
IN
STD_LOGIC
:
=
'1'
;
clock
:
IN
STD_LOGIC
:
=
'1'
;
q
:
OUT
STD_LOGIC_VECTOR
(
31
DOWNTO
0
));
end
alt_mf_rom
;
architecture
fake
of
alt_mf_rom
is
begin
-- fake
q
<=
(
others
=>
'X'
);
end
fake
;
-- -----------------------------------------------------------------------
-- PLL for CPU clocks ----------------------------------------------------
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
...
...
cMIPS/vhdl/cache.vhd
View file @
8cb5a972
...
...
@@ -398,34 +398,7 @@ end behavioral;
-- fake data cache -- pass along all signals unchanged
-- TODO:
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
work
.
p_wires
.
all
;
entity
fake_D_CACHE
is
port
(
rst
:
in
std_logic
;
clk4x
:
in
std_logic
;
cpu_sel
:
in
std_logic
;
-- active in '0'
cpu_rdy
:
out
std_logic
;
-- active in '0'
cpu_wr
:
in
std_logic
;
-- active in '0'
cpu_addr
:
in
std_logic_vector
;
cpu_data_inp
:
in
reg32
;
-- data from CPU
cpu_data_out
:
out
reg32
;
-- data to CPU
cpu_xfer
:
in
std_logic_vector
;
mem_sel
:
out
std_logic
;
-- active in '0'
mem_rdy
:
in
std_logic
;
-- active in '0'
mem_wr
:
out
std_logic
;
-- active in '0'
mem_addr
:
out
std_logic_vector
;
mem_data_inp
:
in
reg32
;
-- data from memory
mem_data_out
:
out
reg32
;
-- data to memory
mem_xfer
:
out
std_logic_vector
;
ref_cnt
:
out
integer
;
rd_hit_cnt
:
out
integer
;
wr_hit_cnt
:
out
integer
;
flush_cnt
:
out
integer
);
end
entity
fake_D_CACHE
;
architecture
behavioral
of
fake_D_CACHE
is
architecture
fake
of
D_CACHE
is
begin
mem_sel
<=
cpu_sel
;
cpu_rdy
<=
mem_rdy
;
...
...
@@ -443,7 +416,7 @@ begin
rd_hit_cnt
<=
0
;
wr_hit_cnt
<=
0
;
flush_cnt
<=
0
;
end
behavioral
;
end
fake
;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
...
...
@@ -696,27 +669,7 @@ end behavioral;
-- fake instruction cache -- pass along all signals unchanged
-- TODO:
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
work
.
p_wires
.
all
;
entity
fake_I_CACHE
is
port
(
rst
:
in
std_logic
;
clk4x
:
in
std_logic
;
ic_reset
:
out
std_logic
;
-- active in '0'
cpu_sel
:
in
std_logic
;
-- active in '0'
cpu_rdy
:
out
std_logic
;
-- active in '0'
cpu_addr
:
in
reg32
;
cpu_data
:
out
reg32
;
mem_sel
:
out
std_logic
;
-- active in '0'
mem_rdy
:
in
std_logic
;
-- active in '0'
mem_addr
:
out
reg32
;
mem_data
:
in
reg32
;
ref_cnt
:
out
integer
;
hit_cnt
:
out
integer
);
end
entity
fake_I_CACHE
;
architecture
behavioral
of
fake_I_CACHE
is
architecture
fake
of
I_CACHE
is
begin
ic_reset
<=
'1'
;
mem_sel
<=
cpu_sel
;
...
...
@@ -726,5 +679,5 @@ begin
ref_cnt
<=
0
;
hit_cnt
<=
0
;
end
behavioral
;
end
fake
;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
cMIPS/vhdl/fpu.vhd
View file @
8cb5a972
...
...
@@ -105,6 +105,9 @@ begin
-- denormB <= '0' when to_integer(unsigned(in_b(30 downto 23))) = 0 else '1';
end
estrutural
;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library
IEEE
;
...
...
@@ -200,6 +203,8 @@ begin
end
process
check_sig
;
end
estrutural
;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
...
...
@@ -414,8 +419,6 @@ end estrutural;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
...
...
@@ -784,6 +787,7 @@ end estrutural;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- FPU
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
...
...
@@ -802,7 +806,7 @@ entity FPU is
data_out
:
out
reg32
);
end
FPU
;
architecture
estrutura
l
of
FPU
is
architecture
rt
l
of
FPU
is
component
wait_states
is
generic
(
NUM_WAIT_STATES
:
integer
);
...
...
@@ -892,30 +896,17 @@ begin
RES_SUM
when
selC_sum
=
'1'
else
(
others
=>
'X'
);
--RES_DIV when selC_div = '1' else
end
estrutura
l
;
end
rt
l
;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- fake_FPU
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
work
.
p_wires
.
all
;
entity
fake_FPU
is
port
(
rst
:
in
std_logic
;
clk
:
in
std_logic
;
sel
:
in
std_logic
;
rdy
:
out
std_logic
;
wr
:
in
std_logic
;
addr
:
in
std_logic_vector
;
data_inp
:
in
reg32
;
data_out
:
out
reg32
);
end
fake_FPU
;
architecture
estrutural
of
fake_FPU
is
architecture
fake
of
FPU
is
begin
rdy
<=
'1'
;
data_out
<=
(
others
=>
'X'
);
end
estrutural
;
end
architecture
fake
;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
cMIPS/vhdl/macnica.vhd
View file @
8cb5a972
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--
-- The components below were adapted from Macnica's Mercurio IV lab material
--
-- ---------------------------------------------------------
...
...
@@ -146,3 +167,4 @@ begin -- rtl
end
rtl
;
-- ----------------------------------------------------------------------
cMIPS/vhdl/memory.vhd
deleted
100644 → 0
View file @
64d9cccb
This diff is collapsed.
Click to expand it.
cMIPS/vhdl/packageMemory.vhd
View file @
8cb5a972
...
...
@@ -58,8 +58,11 @@ package p_MEMORY is
constant
INST_BASE_ADDR
:
integer
:
=
to_integer
(
signed
(
x_INST_BASE_ADDR
));
constant
INST_MEM_SZ
:
integer
:
=
to_integer
(
signed
(
x_INST_MEM_SZ
));
constant
INST_ADDRS_BITS
:
natural
:
=
log2_ceil
(
INST_MEM_SZ
);
constant
DATA_BASE_ADDR
:
integer
:
=
to_integer
(
signed
(
x_DATA_BASE_ADDR
));
constant
DATA_MEM_SZ
:
integer
:
=
to_integer
(
signed
(
x_DATA_MEM_SZ
));
constant
IO_BASE_ADDR
:
integer
:
=
to_integer
(
signed
(
x_IO_BASE_ADDR
));
constant
IO_MEM_SZ
:
integer
:
=
to_integer
(
signed
(
x_IO_MEM_SZ
));
constant
IO_ADDR_RANGE
:
integer
:
=
to_integer
(
signed
(
x_IO_ADDR_RANGE
));
...
...
cMIPS/vhdl/ram.vhd
View file @
8cb5a972
...
...
@@ -26,7 +26,7 @@ use IEEE.numeric_std.all;
use
work
.
p_wires
.
all
;
use
work
.
p_memory
.
all
;
entity
fpga_
RAM
is
entity
RAM
is
generic
(
LOAD_FILE_NAME
:
string
:
=
"data.bin"
;
DUMP_FILE_NAME
:
string
:
=
"dump.data"
);
port
(
rst
:
in
std_logic
;
...
...
@@ -40,13 +40,18 @@ entity fpga_RAM is
data_out
:
out
reg32
;
byte_sel
:
in
reg4
;
dump_ram
:
in
std_logic
);
-- dump RAM contents
-- simulation version
constant
DATA_ADDRS_BITS
:
natural
:
=
log2_ceil
(
DATA_MEM_SZ
);
-- FPGA version
constant
N_WORDS
:
natural
:
=
8192
;
constant
ADDRS_BITS
:
natural
:
=
log2_ceil
(
N_WORDS
);
subtype
ram_address
is
integer
range
0
to
N_WORDS
-1
;
subtype
ram_addr_bits
is
std_logic_vector
(
ADDRS_BITS
-1
downto
0
);
end
entity
fpga_
RAM
;
end
entity
RAM
;
architecture
rtl
of
fpga_
RAM
is
architecture
rtl
of
RAM
is
component
mf_ram1port
generic
(
N_WORDS
:
integer
;
ADDRS_BITS
:
integer
);
...
...
@@ -215,3 +220,184 @@ begin -- rtl
end
architecture
rtl
;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM; initialization Data loaded at CPU reset, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture
simulation
of
RAM
is
component
wait_states
is
generic
(
NUM_WAIT_STATES
:
integer
:
=
0
);
port
(
rst
:
in
std_logic
;
clk
:
in
std_logic
;
sel
:
in
std_logic
;
-- active in '0'
waiting
:
out
std_logic
);
-- active in '1'
end
component
wait_states
;
component
FFT
is
port
(
clk
,
rst
,
T
:
in
std_logic
;
Q
:
out
std_logic
);
end
component
FFT
;
constant
WAIT_COUNT
:
max_wait_states
:
=
NUM_MAX_W_STS
-
RAM_WAIT_STATES
;
signal
wait_counter
,
ram_current
:
integer
;
subtype
t_address
is
unsigned
((
DATA_ADDRS_BITS
-
1
)
downto
0
);
subtype
word
is
std_logic_vector
(
7
downto
0
);
type
storage_array
is
array
(
natural
range
0
to
(
DATA_MEM_SZ
-
1
))
of
word
;
signal
storage
:
storage_array
;
signal
enable
,
waiting
,
do_wait
:
std_logic
;
begin
-- simulation
U_BUS_WAIT
:
wait_states
generic
map
(
RAM_WAIT_STATES
)
port
map
(
rst
,
clk
,
sel
,
waiting
);
rdy
<=
not
(
waiting
);
enable
<=
not
(
sel
);
-- and not(waiting);
accessRAM
:
process
(
strobe
,
enable
,
wr
,
rst
,
addr
,
byte_sel
,
data_inp
,
dump_ram
)
variable
u_addr
:
t_address
;
variable
index
,
latched
:
natural
;
type
binary_file
is
file
of
integer
;
file
load_file
:
binary_file
open
read_mode
is
LOAD_FILE_NAME
;
variable
datum
:
integer
;
variable
s_datum
:
signed
(
31
downto
0
);
file
dump_file
:
binary_file
open
write_mode
is
DUMP_FILE_NAME
;
variable
d
:
reg32
:
=
(
others
=>
'X'
);
variable
val
,
i
:
integer
;
begin
if
rst
=
'0'
then
-- reset, read-in binary initialized data
index
:
=
0
;
-- byte indexed
for
i
in
0
to
(
DATA_MEM_SZ
-
1
)
loop
if
not
endfile
(
load_file
)
then
read
(
load_file
,
datum
);
s_datum
:
=
to_signed
(
datum
,
32
);
-- assert false report "ramINIT["& natural'image(index*4)&"]= " &
-- SLV32HEX(std_logic_vector(s_datum)); -- DEBUG
storage
(
index
+
3
)
<=
std_logic_vector
(
s_datum
(
31
downto
24
));
storage
(
index
+
2
)
<=
std_logic_vector
(
s_datum
(
23
downto
16
));
storage
(
index
+
1
)
<=
std_logic_vector
(
s_datum
(
15
downto
8
));
storage
(
index
+
0
)
<=
std_logic_vector
(
s_datum
(
7
downto
0
));
index
:
=
index
+
4
;
end
if
;
end
loop
;
data_out
<=
(
others
=>
'X'
);
else
-- (rst = '1'), normal operation
-- to simplify (and accelerate) internal address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address that is larger the RAM capacity. Otherwise, the
-- base must be subtracted from the address on every reference,
-- which means having an adder in the critical path. Bad idea.
u_addr
:
=
unsigned
(
addr
(
(
DATA_ADDRS_BITS
-1
)
downto
0
)
);
index
:
=
to_integer
(
u_addr
);
if
sel
=
'0'
and
wr
=
'0'
and
rising_edge
(
strobe
)
then
assert
(
index
>=
0
)
and
(
index
<
DATA_MEM_SZ
)
report
"ramWR index out of bounds: "
&
natural
'image
(
index
)
severity
failure
;
case
byte_sel
is
when
b"1111"
=>
-- SW
storage
(
index
+
3
)
<=
data_inp
(
31
downto
24
);
storage
(
index
+
2
)
<=
data_inp
(
23
downto
16
);
storage
(
index
+
1
)
<=
data_inp
(
15
downto
8
);
storage
(
index
+
0
)
<=
data_inp
(
7
downto
0
);
when
b"1100"
|
b"0011"
=>
-- SH
storage
(
index
+
1
)
<=
data_inp
(
15
downto
8
);
storage
(
index
+
0
)
<=
data_inp
(
7
downto
0
);
when
b"0001"
|
b"0010"
|
b"0100"
|
b"1000"
=>
-- SB
storage
(
index
+
0
)
<=
data_inp
(
7
downto
0
);
when
others
=>
null
;
end
case
;
-- assert false report "ramWR["& natural'image(index) &"] "
-- & SLV32HEX(data) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
end
if
;
-- is write?
if
sel
=
'0'
and
wr
=
'1'
then
assert
(
index
>=
0
)
and
(
index
<
DATA_MEM_SZ
)
report
"ramRD index out of bounds: "
&
natural
'image
(
index
)
severity
failure
;
case
byte_sel
is
when
b"1111"
=>
-- LW
d
(
31
downto
24
)
:
=
storage
(
index
+
3
);
d
(
23
downto
16
)
:
=
storage
(
index
+
2
);
d
(
15
downto
8
)
:
=
storage
(
index
+
1
);
d
(
7
downto
0
)
:
=
storage
(
index
+
0
);
when
b"1100"
=>
-- LH top-half
d
(
31
downto
24
)
:
=
storage
(
index
+
1
);
d
(
23
downto
16
)
:
=
storage
(
index
+
0
);
d
(
15
downto
0
)
:
=
(
others
=>
'X'
);
when
b"0011"
=>
-- LH bottom-half
d
(
31
downto
16
)
:
=
(
others
=>
'X'
);
d
(
15
downto
8
)
:
=
storage
(
index
+
1
);
d
(
7
downto
0
)
:
=
storage
(
index
+
0
);
when
b"0001"
=>
-- LB top byte
d
(
31
downto
8
)
:
=
(
others
=>
'X'
);
d
(
7
downto
0
)
:
=
storage
(
index
+
0
);
when
b"0010"
=>
-- LB mid-top byte
d
(
31
downto
16
)
:
=
(
others
=>
'X'
);
d
(
15
downto
8
)
:
=
storage
(
index
+
0
);
d
(
7
downto
0
)
:
=
(
others
=>
'X'
);
when
b"0100"
=>
-- LB mid-bot byte
d
(
31
downto
24
)
:
=
(
others
=>
'X'
);
d
(
23
downto
16
)
:
=
storage
(
index
+
0
);
d
(
15
downto
0
)
:
=
(
others
=>
'X'
);
when
b"1000"
=>
-- LB bottom byte
d
(
31
downto
24
)
:
=
storage
(
index
+
0
);
d
(
23
downto
0
)
:
=
(
others
=>
'X'
);
when
others
=>
d
:
=
(
others
=>
'X'
);
end
case
;
-- assert false report "ramRD["& natural'image(index) &"] "
-- & SLV32HEX(d) &" bySel="& SLV2STR(byte_sel); -- DEBUG
elsif
rising_edge
(
dump_ram
)
then
i
:
=
0
;
while
i
<
DATA_MEM_SZ
-4
loop
d
(
31
downto
24
)
:
=
storage
(
i
+
3
);
d
(
23
downto
16
)
:
=
storage
(
i
+
2
);
d
(
15
downto
8
)
:
=
storage
(
i
+
1
);
d
(
7
downto
0
)
:
=
storage
(
i
+
0
);
write
(
dump_file
,
to_integer
(
signed
(
d
))
);
i
:
=
i
+
4
;
end
loop
;
-- i
else
d
:
=
(
others
=>
'X'
);
end
if
;
-- is read?
data_out
<=
d
;
end
if
;
-- is reset?
end
process
accessRAM
;
-- ---------------------------------------------
end
architecture
simulation
;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
cMIPS/vhdl/rom.vhd
View file @
8cb5a972
This diff is collapsed.
Click to expand it.
cMIPS/vhdl/sdram.vhd
View file @
8cb5a972
...
...
@@ -436,37 +436,8 @@ end simple;
-- fake SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
work
.
p_wires
.
all
;
entity
fake_SDRAM_controller
is
port
(
rst
:
in
std_logic
;
-- FPGA reset (=0)
clk2x
:
in
std_logic
;
-- 100MHz clock
hcs
:
in
std_logic
;
-- host side chip select (=0)
rdy
:
out
std_logic
;
-- tell CPU to wait (=0)
wr
:
in
std_logic
;
-- host side write enable (=0)
bsel
:
in
reg4
;
-- byte select
haddr
:
in
reg26
;
-- host side address
hDinp
:
in
reg32
;
-- host side data input
hDout
:
out
reg32
;
-- host side data output
cke
:
out
std_logic
;
-- ram side clock enable
scs
:
out
std_logic
;
-- ram side chip select
ras
:
out
std_logic
;
-- ram side RAS
cas
:
out
std_logic
;
-- ram side CAS
we
:
out
std_logic
;
-- ram side write enable
dqm0
:
out
std_logic
;
-- ram side byte0 output enable
dqm1
:
out
std_logic
;
-- ram side byte0 output enable
ba0
:
out
std_logic
;
-- ram side bank select 0
ba1
:
out
std_logic
;
-- ram side bank select 1
saddr
:
out
reg12
;
-- ram side address
sdata
:
inout
reg16
);
-- ram side data
end
entity
fake_SDRAM_controller
;
architecture
fake
of
fake_SDRAM_controller
is
architecture
fake
of
SDRAM_controller
is
begin
rdy
<=
'1'
;
...
...
@@ -486,3 +457,4 @@ begin
end
architecture
fake
;
-- ---------------------------------------------------------------------
cMIPS/vhdl/tb_cMIPS.vhd
View file @
8cb5a972
...
...
@@ -155,17 +155,6 @@ architecture TB of tb_cMIPS is
data_out
:
out
std_logic_vector
);
end
component
FPU
;
component
fake_FPU
is
port
(
rst
:
in
std_logic
;
clk
:
in
std_logic
;
sel
:
in
std_logic
;
rdy
:
out
std_logic
;
wr
:
in
std_logic
;
addr
:
in
std_logic_vector
;
data_inp
:
in
std_logic_vector
;
data_out
:
out
std_logic_vector
);
end
component
fake_FPU
;
component
remota
is
generic
(
OUTPUT_FILE_NAME
:
string
;
INPUT_FILE_NAME
:
string
);
port
(
rst
,
clk
:
in
std_logic
;
...
...
@@ -246,7 +235,7 @@ architecture TB of tb_cMIPS is
data
:
out
std_logic_vector
);
end
component
simul_ROM
;
component
fpga_
ROM
is
component
ROM
is
generic
(
LOAD_FILE_NAME
:
string
);
port
(
rst
:
in
std_logic
;
clk
:
in
std_logic
;
...
...
@@ -255,9 +244,9 @@ architecture TB of tb_cMIPS is
strobe
:
in
std_logic
;
addr
:
in
std_logic_vector
;
data
:
out
std_logic_vector
);
end
component
fpga_
ROM
;
end
component
ROM
;
component
simul_
RAM
is
component
RAM
is
generic
(
LOAD_FILE_NAME
:
string
;
DUMP_FILE_NAME
:
string
);
port
(
rst
:
in
std_logic
;
clk
:
in
std_logic
;
...
...
@@ -270,7 +259,7 @@ architecture TB of tb_cMIPS is
data_out
:
out
std_logic_vector
;
byte_sel
:
in
std_logic_vector
;
dump_ram
:
in
std_logic
);
end
component
simul_
RAM
;
end
component
RAM
;
component
fpga_RAM
is
generic
(
LOAD_FILE_NAME
:
string
;
DUMP_FILE_NAME
:
string
);
...
...
@@ -310,45 +299,6 @@ architecture TB of tb_cMIPS is
sdata
:
inout
reg16
);
-- ram side data
end
component
SDRAM_controller
;
component
fake_SDRAM_controller
is
port
(
rst
:
in
std_logic
;
-- FPGA reset (=0)
clk2x
:
in
std_logic
;
-- 100MHz clock
hcs
:
in
std_logic
;
-- host side chip select (=0)
rdy
:
out
std_logic
;
-- tell CPU to wait (=0)
wr
:
in
std_logic
;
-- host side write enable (=0)
bsel
:
in
reg4
;
-- byte select
haddr
:
in
reg26
;
-- host side address
hDinp
:
in
reg32
;
-- host side data input
hDout
:
out
reg32
;
-- host side data output
cke
:
out
std_logic
;
-- ram side clock enable
scs
:
out
std_logic
;
-- ram side chip select
ras
:
out
std_logic
;
-- ram side RAS
cas
:
out
std_logic
;
-- ram side CAS
we
:
out
std_logic
;
-- ram side write enable
dqm0
:
out
std_logic
;
-- ram side byte0 output enable
dqm1
:
out
std_logic
;
-- ram side byte0 output enable
ba0
:
out
std_logic
;
-- ram side bank select 0
ba1
:
out
std_logic
;
-- ram side bank select 1
saddr
:
out
reg12
;
-- ram side address
sdata
:
inout
reg16
);
-- ram side data
end
component
fake_SDRAM_controller
;
component
fake_I_CACHE
is
port
(
rst
:
in
std_logic
;
clk4x
:
in
std_logic
;
ic_reset
:
out
std_logic
;
cpu_sel
:
in
std_logic
;
cpu_rdy
:
out
std_logic
;
cpu_addr
:
in
std_logic_vector
;
cpu_data
:
out
std_logic_vector
;
mem_sel
:
out
std_logic
;
mem_rdy
:
in
std_logic
;
mem_addr
:
out
std_logic_vector
;
mem_data
:
in
std_logic_vector
;
ref_cnt
:
out
integer
;
hit_cnt
:
out
integer
);
end
component
fake_I_CACHE
;
component
I_CACHE
is
port
(
rst
:
in
std_logic
;
clk4x
:
in
std_logic
;
...
...
@@ -381,29 +331,6 @@ architecture TB of tb_cMIPS is
hit_cnt
:
out
integer
);
end
component
I_CACHE_fpga
;
component
fake_D_CACHE
is
port
(
rst
:
in
std_logic
;
clk4x
:
in
std_logic
;
cpu_sel
:
in
std_logic
;
cpu_rdy
:
out
std_logic
;
cpu_wr
:
in
std_logic
;
cpu_addr
:
in
std_logic_vector
;
cpu_data_inp
:
in
std_logic_vector
;
cpu_data_out
:
out
std_logic_vector
;
cpu_xfer
:
in
std_logic_vector
;
mem_sel
:
out
std_logic
;
mem_rdy
:
in
std_logic
;
mem_wr
:
out
std_logic
;
mem_addr
:
out
std_logic_vector
;
mem_data_inp
:
in
std_logic_vector
;
mem_data_out
:
out
std_logic_vector
;
mem_xfer
:
out
std_logic_vector
;
ref_cnt
:
out
integer
;
rd_hit_cnt
:
out
integer
;
wr_hit_cnt
:
out
integer
;
flush_cnt
:
out
integer
);
end
component
fake_D_CACHE
;
component
D_CACHE
is
port
(
rst
:
in
std_logic
;
clk4x
:
in
std_logic
;
...
...
@@ -601,15 +528,13 @@ begin -- TB
U_INST_ADDR_DEC
:
inst_addr_decode
port
map
(
rst
,
cpu_i_aVal
,
i_addr
,
inst_aVal
,
i_busError
);
U_I_CACHE
:
fake_i_cache
-- or i_cache
-- U_I_CACHE: i_cache -- or fake_i_cache
-- U_I_CACHE: i_cache_fpga -- or FPGA implementation
U_I_CACHE
:
i_cache
port
map
(
rst
,
clk4x
,
ic_reset
,
inst_aVal
,
inst_wait
,
i_addr
,
cpu_instr
,
mem_i_sel
,
rom_rdy
,
mem_i_addr
,
datrom
,
cnt_i_ref
,
cnt_i_hit
);
U_ROM
:
simul_ROM
generic
map
(
"prog.bin"
)
-- U_ROM: fpga_ROM generic map ("prog.bin")
U_ROM
:
ROM
generic
map
(
"prog.bin"
)
port
map
(
rst
,
clk
,
mem_i_sel
,
rom_rdy
,
phi3
,
mem_i_addr
,
datrom
);
U_DATA_BUS_ERROR_DEC
:
busError_addr_decode
...
...
@@ -639,8 +564,7 @@ begin -- TB
lcd_d_out
when
b"1101"
,
(
others
=>
'X'
)
when
others
;
U_D_CACHE
:
fake_d_cache
-- or d_cache
-- U_D_CACHE: d_cache -- or fake_d_cache
U_D_CACHE
:
d_cache
port
map
(
rst
,
clk4x
,
data_aVal
,
data_wait
,
wr
,
d_addr
,
cpu_data
,
d_cache_d_out
,
cpu_xfer
,
...
...
@@ -648,13 +572,11 @@ begin -- TB
mem_addr
,
datram_inp
,
datram_out
,
mem_xfer
,
cnt_d_ref
,
cnt_d_rd_hit
,
cnt_d_wr_hit
,
cnt_d_flush
);