remote UART now activated by RTS

cMIPS/bin/assemble.sh

@@ -126,6 +126,6 @@ dat=data.bin
 
   fi
 
-# -M reg-names=mips2r2 -M cp0-names=mips2r2 \
+# -M reg-names=mips2r2 -M cp0-names=mips2r2 reg-names=numeric \
 #        --section .reginfo
 

cMIPS/bin/build.sh

@@ -66,7 +66,7 @@ simulator=tb_cmips
 
 pkg="packageWires.vhd packageMemory.vhd packageExcp.vhd"
 
-src="aux.vhd altera.vhd macnica.vhd memory.vhd cache.vhd instrcache.vhd sdram.vhd ram.vhd rom.vhd units.vhd io.vhd uart.vhd fpu.vhd pipestages.vhd exception.vhd core.vhd tb_cMIPS.vhd"
+src="aux.vhd altera.vhd macnica.vhd cache.vhd instrcache.vhd sdram.vhd ram.vhd rom.vhd units.vhd io.vhd uart.vhd fpu.vhd pipestages.vhd exception.vhd core.vhd tb_cMIPS.vhd"
 
 # build simulator
 #ghdl --clean

cMIPS/tests/doTests.sh

@@ -124,7 +124,7 @@ if [ $withCache = true ] ; then
   SIMULATE="$c_small $c_types $c_sorts"
 else
   SIMULATE="$c_small $c_types $c_sorts $c_FPU $c_timing $c_uart"
-  echo -e "abcdef\n012345\n" >serial.inp
+  echo -e "\nabcdef\n012345\n" >serial.inp
   # make sure all memory latencies are ZERO
   # pack=$srcVHDL/packageWires.vhd
   # sed -i -e "/ROM_WAIT_STATES/s/ := \([0-9][0-9]*\);/ := 0;/" \

cMIPS/tests/uartrx.c

@@ -21,9 +21,6 @@ typedef struct status {  // status register fields (uses only ls byte)
   overun  : 1;           // overun error (bit 0)
 } Tstatus;
 
-#define RXfull  0x00000020
-#define TXempty 0x00000040
-
 
 typedef union ctlStat { // control + status on same address
   Tcontrol  ctl;        // write-only
@@ -57,7 +54,7 @@ int main(void) { // receive a string through the UART serial interface
   uart = (void *)IO_UART_ADDR; // bottom of UART address range
 
   ctrl.ign   = 0;
-  ctrl.rts   = 1;
+  ctrl.rts   = 0;   // make RTS=0 to hold RemoteUnit
   ctrl.ign2  = 0;
   ctrl.intTX = 0;
   ctrl.intRX = 0;
@@ -66,6 +63,14 @@ int main(void) { // receive a string through the UART serial interface
 
   i = -1;
 
+  ctrl.ign   = 0;
+  ctrl.rts   = 1;   // make RTS=1 to activate RemoteUnit
+  ctrl.ign2  = 0;
+  ctrl.intTX = 0;
+  ctrl.intRX = 0;
+  ctrl.speed = 1;   // operate at the second highest data rate
+  uart->cs.ctl = ctrl;
+
   do {
     i = i+1;
 

cMIPS/vhdl/fpu.vhd

@@ -783,7 +783,7 @@ begin
   w_intra <= (wt_in or wt_stg0 or wt_stg1 or wt_stg2) and (not w_pronto) ;
   wt_out <= w_intra;
 
-end estrutural;
+end architecture estrutural;
 -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
 
@@ -806,6 +806,21 @@ entity FPU is
        data_out : out   reg32);
 end FPU;
 
+
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- fake FPU
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+architecture fake of FPU is
+begin
+  rdy <= '1';
+  data_out <= (others => '0');
+end architecture fake;
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- FPU
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 architecture rtl of FPU is
 
   component wait_states is
@@ -896,17 +911,7 @@ begin
               RES_SUM when selC_sum = '1' else
               (others => 'X');
               --RES_DIV when selC_div = '1' else
-end rtl;
+end architecture rtl;
 -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
 
-
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--- fake_FPU
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-architecture fake of FPU is
-begin
-  rdy <= '1';
-  data_out <= (others => 'X');
-end architecture fake;
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

cMIPS/vhdl/io.vhd

@@ -522,6 +522,7 @@ architecture behavioral of to_7seg is
   end component display_7seg;
   
   signal value : std_logic_vector(NUM_BITS-1 downto 0);
+  signal middle : std_logic;
   
 begin
   
@@ -532,10 +533,12 @@ begin
 
   U_DSP0: display_7seg port map (value(3 downto 0), value(8), display0);
 
-  U_sim: process(sel,rst)
+
+  U_sim: process(sel,rst,clk)
   begin
+    middle <= not(sel) and not(clk); -- to remove spurious reports
     if rst = '1' then
-      assert not(falling_edge(sel))
+      assert not(rising_edge(middle))
         report "dsp7seg: "&  SLV32HEX(data) severity NOTE;
     end if;
   end process;

cMIPS/vhdl/tb_cMIPS.vhd

@@ -439,7 +439,6 @@ architecture TB of tb_cMIPS is
 
   signal dump_ram : std_logic;
   
-  signal start_remota : std_logic;
   signal bit_rt : reg3;
 
   -- Macnica development board's peripherals
@@ -629,16 +628,14 @@ begin  -- TB
               -- uncoment next line for loop back, comment out previous line
               -- uart_txd, uart_txd, uart_rts, uart_cts, uart_irq, bit_rt);
 
-  uart_cts <= '1';
-  
-  start_remota <= '0', '1' after 200*CLOCK_PER;
+  uart_cts <= uart_rts;
   
   U_uart_remota: remota generic map ("serial.out","serial.inp")
-    port map (rst, clk, start_remota, uart_txd, uart_rxd, bit_rt);
+    port map (rst, clk, uart_rts, uart_txd, uart_rxd, bit_rt);
 
   U_FPU: FPU
-    port map (rst,clk, io_FPU_sel,io_FPU_wait, wr, d_addr(5 downto 2),
-              cpu_data,fpu_d_out);
+    port map (rst,clk, io_FPU_sel, io_FPU_wait, wr, d_addr(5 downto 2),
+              cpu_data, fpu_d_out);
 
   -- U_sys_stats: sys_stats                -- CPU reads system counters
   --   port map (cpu_reset,clk, io_sstats_sel, wr, d_addr, sstats_d_out,
@@ -993,7 +990,7 @@ begin
       when  4 => dev_sel     := std_logic_vector(to_signed(is_write, 4));
                  write_sel   <= aVal or clk;
       when  5 => dev_sel     := std_logic_vector(to_signed(is_count, 4));
-                 counter_sel <= aVal;
+                 counter_sel <= aVal or clk;
       when  6 => dev_sel     := std_logic_vector(to_signed(is_FPU, 4));
                  FPU_sel     <= aVal;
       when  7 => dev_sel     := std_logic_vector(to_signed(is_UART, 4));
@@ -1046,10 +1043,9 @@ configuration CFG_TB of TB_CMIPS is
       use entity work.D_cache(fake);
     end for;
 
-
     -- use fake / rtl
     for U_FPU: FPU
-      use entity work.FPU(fake);
+      use entity work.FPU(rtl);
     end for;
     
     -- use fake / simple
@@ -1057,7 +1053,6 @@ configuration CFG_TB of TB_CMIPS is
       use entity work.SDRAM_controller(fake);
     end for;
 
-
   end for;
 end configuration CFG_TB;
 -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

cMIPS/vhdl/uart.vhd

@@ -753,10 +753,14 @@ end functional;
 
 
 
+
+
 -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 -- functional model for the "remote computer" -- for testing only
 -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
 use std.textio.all;
 use work.p_WIRES.all;