Commit f053542d authored by Roberto Hexsel's avatar Roberto Hexsel

added sdram address decoding

parent de9f9e78
Pipeline #2516 skipped
......@@ -56,7 +56,7 @@ hdr="${include}"/cMIPS.h
asm="${include}"/cMIPS.s
VARIABLES="x_INST_BASE_ADDR x_INST_MEM_SZ x_DATA_BASE_ADDR x_DATA_MEM_SZ x_IO_BASE_ADDR x_IO_MEM_SZ x_IO_ADDR_RANGE"
VARIABLES="x_INST_BASE_ADDR x_INST_MEM_SZ x_DATA_BASE_ADDR x_DATA_MEM_SZ x_IO_BASE_ADDR x_IO_MEM_SZ x_IO_ADDR_RANGE x_SDRAM_BASE_ADDR x_SDRAM_MEM_SZ"
EXCEPTION_VECTORS="x_EXCEPTION_0000 x_EXCEPTION_0100 x_EXCEPTION_0180 x_EXCEPTION_0200 x_EXCEPTION_BFC0 x_ENTRY_POINT"
......
#define x_INST_BASE_ADDR 0x00000000
#define x_DATA_BASE_ADDR 0x00010000
#define x_IO_BASE_ADDR 0x0F000000
#define x_IO_MEM_SZ 0x00002000
#define x_IO_ADDR_RANGE 0x00000020
#define x_INST_BASE_ADDR 0x00000000
#define x_DATA_BASE_ADDR 0x00010000
#define x_SDRAM_BASE_ADDR 0x04000000
#define x_SDRAM_MEM_SZ 0x02000000
#define x_IO_BASE_ADDR 0x3c000000
#define x_IO_MEM_SZ 0x00002000
#define x_IO_ADDR_RANGE 0x00000020
#define x_IO_ADDR_MASK (0 - x_IO_ADDR_RANGE)
......
......@@ -7,7 +7,9 @@ MEMORY
LENGTH = 0x00004000, /* x_INST_MEM_SZ */
ram (!rx) : ORIGIN = 0x00010000, /* x_DATA_BASE_ADDR */
LENGTH = 0x00008000, /* x_DATA_MEM_SZ */
io (!rx) : ORIGIN = 0x0f000000, /* not used, do not remove */
sdram (!rx) : ORIGIN = 0x04000000, /* x_SDRAM_BASE_ADDR */
LENGTH = 0x02000000, /* x_SDRAM_MEM_SZ */
io (!rx) : ORIGIN = 0x3c000000, /* not used, do not remove */
LENGTH = 0x00020000 /* edMemory.sh needs thess lines */
}
......
......@@ -6,10 +6,13 @@
.set x_DATA_BASE_ADDR,0x00010000
.set x_DATA_MEM_SZ,0x00008000
.set x_IO_BASE_ADDR,0x0F000000
.set x_IO_BASE_ADDR,0x3c000000
.set x_IO_MEM_SZ,0x00002000
.set x_IO_ADDR_RANGE,0x00000020
.set x_SDRAM_BASE_ADDR,0x04000000
.set x_SDRAM_MEM_SZ,0x02000000
.set HW_counter_addr,(x_IO_BASE_ADDR + 5 * x_IO_ADDR_RANGE)
.set HW_FPU_addr, (x_IO_BASE_ADDR + 6 * x_IO_ADDR_RANGE)
.set HW_uart_addr, (x_IO_BASE_ADDR + 7 * x_IO_ADDR_RANGE)
......
# Test SDRAM's address range
# read from 4 distinct sdram rows
.include "cMIPS.s"
.text
.align 2
.set noreorder
.globl _start
.ent _start
.set HW_stdout_addr,(x_IO_BASE_ADDR + 1 * x_IO_ADDR_RANGE)
.set SDRAM_base,x_SDRAM_BASE_ADDR
.set S_row,(8*4)
_start: nop
la $20, HW_stdout_addr
la $10, SDRAM_base
snd: lw $3, 0($10)
li $5, 1
li $5, 2
lw $3, 1*S_row($10)
li $5, 3
li $5, 4
lw $3, 2*S_row($10)
li $5, 5
li $5, 6
lw $3, 3*S_row($10)
li $5, 7
li $5, 8
li $5, 9
li $5, 10
end: nop
nop
nop
nop
nop
wait 0
nop
nop
.end _start
......@@ -3011,14 +3011,14 @@ begin
-- TLB entry 6 -- initialized to 5th,6th pages of RAM
-- TLB entry 6 -- initialized to 1st,2nd pages of SDRAM
MMU_TAG6: register32 generic map(MMU_ini_tag_RAM4)
MMU_TAG6: register32 generic map(MMU_ini_tag_SDR0)
port map (clk, rst, tlb_tag6_updt, tlb_tag_inp, tlb_tag6);
MMU_DAT6_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM4) -- d=1,v=1,g=1
MMU_DAT6_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_SDR0) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat6_updt, tlb_dat0_inp, tlb_dat6_0);
MMU_DAT6_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM5) -- d=1,v=1,g=1
MMU_DAT6_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_SDR1) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat6_updt, tlb_dat1_inp, tlb_dat6_1);
hit6_pc <= TRUE when (tlb_tag6(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
......
......@@ -204,7 +204,8 @@ package p_MEMORY is
constant DAT_AHI_BIT : natural := DAT_ALO_BIT + PPN_BITS - 1;
constant DAT_REG_BITS : natural := DAT_ALO_BIT + PPN_BITS;
constant ContextPTE_init : reg9 := b"000000000";
constant ContextPTE_init : reg9 := b"000000000";
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
subtype mmu_dat_reg is std_logic_vector (DAT_AHI_BIT downto 0);
......@@ -256,7 +257,7 @@ package p_MEMORY is
x_ROM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 ROM pages
-- physical addresses for 8 RAM pages
constant x_RAM_PPN_0 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_RAM_PPN_1 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 1*PAGE_SZ, 32));
......@@ -303,8 +304,41 @@ package p_MEMORY is
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
x_IO_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 SDRAM pages
constant x_SDRAM_PPN_0 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_SDRAM_PPN_1 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_SDRAM_PPN_2 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_SDRAM_PPN_3 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_SDRAM_PPN_4 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_SDRAM_PPN_5 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_SDRAM_PPN_6 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_SDRAM_PPN_7 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 7*PAGE_SZ, 32));
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
constant MMU_ini_tag_SDR0 : reg32 := (x_SDRAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR0 : mmu_dat_reg :=
x_SDRAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR1 : mmu_dat_reg :=
x_SDRAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR2 : reg32 := (x_SDRAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR2 : mmu_dat_reg :=
x_SDRAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR3 : mmu_dat_reg :=
x_SDRAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR4 : reg32 := (x_SDRAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR4 : mmu_dat_reg :=
x_SDRAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR5 : mmu_dat_reg :=
x_SDRAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR6 : reg32 := (x_SDRAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR6 : mmu_dat_reg :=
x_SDRAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR7 : mmu_dat_reg :=
x_SDRAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
end p_MEMORY;
......
......@@ -34,9 +34,10 @@ use work.p_memory.all;
entity SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
hcs : in std_logic; -- host side chip select (=0)
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
......@@ -94,32 +95,6 @@ entity SDRAM_controller is
end entity SDRAM_controller;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- fake SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SDRAM_controller is
begin
rdy <= '1';
hDout <= (others => 'X');
cke <= '1';
scs <= '1';
ras <= '1';
cas <= '1';
we <= '1';
dqm0 <= '1';
dqm1 <= '1';
ba0 <= '1';
ba1 <= '1';
saddr <= (others => 'X');
sdata <= (others => 'X');
end architecture fake;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- real SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
......@@ -150,6 +125,19 @@ architecture simple of SDRAM_controller is
Q: out std_logic_vector);
end component registerN;
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
-- state machine
type ctrl_state is
(st_noreset, -- 0
......@@ -179,9 +167,24 @@ architecture simple of SDRAM_controller is
signal ld_old : std_logic;
signal command : t_cmd_type;
signal doit : cmd_index;
signal wait1, wait2, waiting : std_logic;
begin -- simple
U_WAIT_ON_READS: wait_states generic map (1)
port map (rst, clk, sel, wait1);
U_WAIT2: FFDsimple port map (clk, rst, wait1, wait2);
rdy <= not BOOL2SL((sel = '0') and
((wait1 = '1') or (wait2 = '1') or (waiting = '1')));
is_accs <= (sel = '0');
is_rd <= (sel = '0') and (wr = '1');
is_wr <= (sel = '0') and (wr = '0');
command <= cmd_table(doit);
scs <= command.cs;
ras <= command.ras;
......@@ -197,7 +200,7 @@ begin -- simple
addr(9 downto 0);
U_address: registerN generic map (26, b"00"&x"000000")
port map (clk2x, rst, hcs, haddr, addr);
port map (clk2x, rst, sel, haddr, addr);
row_bits <= addr(23 downto 11);
col_bits <= addr(10 downto 1);
......@@ -205,11 +208,12 @@ begin -- simple
ba1 <= addr(25);
ld_old <= hcs and not(BOOL2SL(same_row));
ld_old <= sel and not(BOOL2SL(same_row));
U_last_row: registerN generic map (13, '1'&x"fff")
port map (clk2x, rst, ld_old, haddr(23 downto 11), last_row);
same_row <= (last_row = row_bits) and (command.cmd /= cPALL);
-- same_row <= (last_row = row_bits) and (command.cmd /= cPALL);
same_row <= FALSE;
......@@ -238,7 +242,7 @@ begin -- simple
else
next_st <= st_noreset;
end if;
-- INITIALIZATION SEQUENCE
when st_in0 => -- 1 nop
next_st <= st_in1;
......@@ -394,7 +398,6 @@ begin -- simple
end case;
end process U_CTRL_st_transitions; ---------------------------
U_CTRL_outputs: process(curr_st) ------------------------------
begin
......@@ -420,10 +423,33 @@ begin -- simple
when others =>
doit <= cNOP;
end case;
end process U_CTRL_outputs; -------------------------------------------
end process U_CTRL_outputs; ----------------------------------
U_CTRL_waiting: process(curr_st) ------------------------------
begin
case curr_st is
when st_rdcol | st_rdn0 =>
waiting <= '0'; -- read from column
when st_wrcol =>
waiting <= '0'; -- write to column
when st_ipre | st_pall =>
waiting <= '0'; -- precharge all banks
when st_aref1 | st_aref2 | st_aref3 | st_aref4 =>
waiting <= '0'; -- auto-refresh
when st_lmr =>
waiting <= '0'; -- load mode register
when st_act | st_an0 | st_an1 =>
waiting <= '0'; -- activate row
when others =>
waiting <= '1';
end case;
end process U_CTRL_waiting; -----------------------------------
......@@ -477,3 +503,29 @@ end simple;
-- ---------------------------------------------------------------------
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- fake SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SDRAM_controller is
begin
rdy <= '1';
hDout <= (others => 'X');
cke <= '1';
scs <= '1';
ras <= '1';
cas <= '1';
we <= '1';
dqm0 <= '1';
dqm1 <= '1';
ba0 <= '1';
ba1 <= '1';
saddr <= (others => 'X');
sdata <= (others => 'X');
end architecture fake;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -259,8 +259,9 @@ architecture TB of tb_cMIPS is
component SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
hcs : in std_logic; -- host side chip select (=0)
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
......@@ -414,7 +415,7 @@ architecture TB of tb_cMIPS is
signal irq : reg6;
signal inst_aVal, inst_wait, rom_rdy : std_logic;
signal data_aVal, data_wait, ram_rdy, mem_wr : std_logic;
signal sdram_aVal, sdram_rdy, sdram_wr : std_logic;
signal sdram_aVal, sdram_wait, sdram_wr : std_logic;
signal cpu_xfer, mem_xfer : reg4;
signal dev_select, dev_select_ram, dev_select_io, dev_select_sdram : reg4;
signal io_print_sel : std_logic := '1';
......@@ -456,24 +457,11 @@ architecture TB of tb_cMIPS is
signal LCD_RS, LCD_RW, LCD_EN, LCD_BLON : std_logic; -- LCD control
signal uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq : std_logic;
signal hcs : std_logic; -- host side chip select (=0)
signal haddr : reg26; -- host side address
signal hDinp : reg32; -- host side data input
signal hDout : reg32; -- host side data output
signal sdcke : std_logic; -- ram side clock enable
signal sdscs : std_logic; -- ram side chip select
signal sdras : std_logic; -- ram side RAS
signal sdcas : std_logic; -- ram side CAS
signal sdwe : std_logic; -- ram side write enable
signal sddqm0 : std_logic; -- ram side byte0 output enable
signal sddqm1 : std_logic; -- ram side byte0 output enable
signal sdba0 : std_logic; -- ram side bank select 0
signal sdba1 : std_logic; -- ram side bank select 1
signal sdaddr : reg12; -- ram side address
signal sddata : reg16; -- ram side data
signal sdcke, sdscs, sdras, sdcas, sdwe : std_logic; -- SDRAM
signal sddqm0, sddqm1, sdba0, sdba1 : std_logic;
signal sdaddr : reg12;
signal sddata : reg16;
signal hDinp, hDout : reg32;
begin -- TB
......@@ -484,7 +472,6 @@ begin -- TB
-- pll_io : mf_altpll_io port map (areset => a_reset, inclk0 => clock_50mhz,
-- c0 => clk2x, c1 => clk4x0, c2 => clk4x180);
clk2x <= '0';
clk4x0 <= '0';
clk4x180 <= '0';
......@@ -514,20 +501,21 @@ begin -- TB
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait;
cpu_d_wait <= data_wait and io_wait and sdram_wait;
io_wait <= io_lcd_wait and io_fpu_wait;
not_waiting <= (inst_wait and data_wait); -- and io_wait);
not_waiting <= (inst_wait and data_wait and sdram_wait); -- and io_wait);
-- irq <= b"000000"; -- NO interrupt requests
irq <= uart_irq & counter_irq & b"0000"; -- uart+counter interrupts
-- irq <= counter_irq & b"00000"; -- counter interrupts
nmi <= '0'; -- input port to TB
U_CORE: core port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, nmi, irq, i_busError, d_busError);
U_CORE: core
port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, nmi, irq, i_busError, d_busError);
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
......@@ -542,7 +530,8 @@ begin -- TB
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
port map (rst, cpu_d_aVal, d_addr, d_busError);
port map (rst, cpu_d_aVal, d_addr, open);
d_busError <= '1'; -- only while testing the SDRAM
U_IO_ADDR_DEC: io_addr_decode
port map (phi0, rst, cpu_d_aVal, d_addr, dev_select_io,
......@@ -585,10 +574,11 @@ begin -- TB
mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
U_SDRAMc: SDRAM_controller port map
(rst, clk, sdram_aVal, sdram_rdy, wr, cpu_xfer, d_addr(25 downto 0),
hDinp,hDout,
(rst, clk, clk2x, sdram_aVal, sdram_wait, wr,
cpu_xfer, d_addr(25 downto 0), hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
sdcke <= '1';
U_to_stdout: to_stdout
port map (rst,clk, io_stdout_sel, wr, cpu_data);
......@@ -657,9 +647,15 @@ begin -- TB
U_clock: process -- simulate external clock
begin
clock_50mhz <= '1';
wait for CLOCK_PER / 2;
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
clock_50mhz <= '0';
wait for CLOCK_PER / 2;
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
end process; -- -------------------------------------------------------
-- simulate reset switch bounces
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment