fixed yesterday-s incomplete update

cMIPS/include/handlers.s

@@ -203,3 +203,57 @@ cmips_delay:
         nop
 	.end    cmips_delay
 	#----------------------------------------------------------------
+
+
+	#----------------------------------------------------------------	
+	# print a message, does not disturbs registers
+	.bss 
+        .align  2
+	.comm   _kmsg_saves 4*4		# area to save up to 4 registers
+	# _kmsg_saves[0]=$a0, [1]=$a1, [2]=$a2, [3]=$ra
+	#
+	.text
+	.set    noreorder
+	.set    noat
+	.global cmips_kmsg
+	.ent    cmips_kmsg
+	.equ	stdout_addr,(x_IO_BASE_ADDR + 1*x_IO_ADDR_RANGE);
+	#  void cmips_kmsg( $k1 )
+cmips_kmsg:
+	lui   $k0, %hi(_kmsg_saves)
+	ori   $k0, $k0, %lo(_kmsg_saves)
+	sw    $a0, 0*4($k0)
+	sw    $a1, 1*4($k0)
+	sw    $a2, 2*4($k0)
+	
+	lui   $a1, %hi(_kmsg_list)
+	ori   $a1, $a1, %hi(_kmsg_list)
+
+	sll   $k1, $k1, 2		# adjust index onto table
+	addu  $a1, $a1, $k1
+
+	lui   $a2, %hi(stdout_addr)
+	ori   $a2, $a2, %lo(stdout_addr)
+	
+k_for:	lbu   $a0, 0($a1)
+	sb    $a0, 0($a2)		# send it to simulator's stdout
+	bne   $a0, $zero, k_for
+	addiu $a1, $a1, 1
+	
+	lw    $a0, 0*4($k0)
+	lw    $a1, 1*4($k0)
+	jr    $ra
+	lw    $a2, 2*4($k0)
+
+	.end    cmips_kmsg
+
+	.equ kmsg_interr,0
+	.equ kmsg_excep,1
+	.data
+	.global _kmsg_list
+_kmsg_list: .word _kmsg_interr,_kmsg_excep
+
+_kmsg_interr:	.asciiz "\n\tinterrupt\n\n"
+_kmsg_excep:	.asciiz "\n\texceptioninterrupt\n\n"
+	#----------------------------------------------------------------
+

cMIPS/vhdl/core.vhd

@@ -3013,12 +3013,12 @@ begin
 
   -- TLB entry 6 -- initialized to 1st,2nd pages of SDRAM
   
-  MMU_TAG6: register32 generic map(MMU_ini_tag_SDR0)
+  MMU_TAG6: register32 generic map(MMU_ini_tag_RAM4)
     port map (clk, rst, tlb_tag6_updt, tlb_tag_inp, tlb_tag6);
 
-  MMU_DAT6_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_SDR0)  -- d=1,v=1,g=1
+  MMU_DAT6_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM4)  -- d=1,v=1,g=1
     port map (clk, rst, tlb_dat6_updt, tlb_dat0_inp, tlb_dat6_0);
-  MMU_DAT6_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_SDR1)  -- d=1,v=1,g=1
+  MMU_DAT6_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM5)  -- d=1,v=1,g=1
     port map (clk, rst, tlb_dat6_updt, tlb_dat1_inp, tlb_dat6_1);
 
   hit6_pc <= TRUE when (tlb_tag6(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)

cMIPS/vhdl/tb_cMIPS.vhd

@@ -530,8 +530,8 @@ begin  -- TB
     port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
 
   U_DATA_BUS_ERROR_DEC: busError_addr_decode
-    port map (rst, cpu_d_aVal, d_addr, open);
-    d_busError <= '1';                  -- only while testing the SDRAM
+    port map (rst, cpu_d_aVal, d_addr, d_busError);
+    -- d_busError <= '1';                  -- only while testing the SDRAM
 
   U_IO_ADDR_DEC: io_addr_decode
     port map (phi0, rst, cpu_d_aVal, d_addr, dev_select_io,