v_rx.sav 1.87 KB
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[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
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[*] Fri Apr  8 16:29:19 2016
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[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
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[dumpfile_mtime] "Fri Apr  8 13:54:30 2016"
[dumpfile_size] 11860622
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[savefile] "/home/roberto/cMIPS/v_rx.sav"
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[timestart] 1652600000
[size] 1133 1018
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[pos] -1 -1
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*-26.000000 1820000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
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[treeopen] u_simple_uart.
[sst_width] 210
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[signals_width] 218
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[sst_expanded] 1
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[sst_vpaned_height] 304
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@28
clk
@22
u_core.pc[31:0]
u_core.instr_fetched[31:0]
@200
-    decode, reg fetch
@22
u_core.regs_a[31:0]
u_core.regs_b[31:0]
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u_core.rf_instruction[31:0]
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@200
-    exec
@24
u_core.u_alu.operation[31:0]
@22
u_core.alu_inp_a[31:0]
u_core.alu_inp_b[31:0]
u_core.result[31:0]
@200
-    memory
@28
u_core.b_sel[3:0]
@22
d_addr[31:0]
@28
cpu_d_aval
u_core.mm_wrmem
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@22
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u_core.data_inp[31:0]
u_core.data_out[31:0]
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@200
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-   UART
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@28
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u_simple_uart.u_uart.rts
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u_simple_uart.u_uart.s_stat
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u_simple_uart.u_uart.status[7:0]
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@22
u_simple_uart.u_uart.status[7:0]
@28
u_simple_uart.u_uart.s_ctrl
u_simple_uart.u_uart.ctrl[7:0]
@200
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-   reception circuit
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@24
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u_simple_uart.u_uart.rxcpu_dbg_st[31:0]
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u_simple_uart.u_uart.rx_dbg_st[31:0]
@29
u_simple_uart.u_uart.s_rx
@22
u_simple_uart.u_uart.rxreg[7:0]
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@28
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u_simple_uart.u_uart.interr_rx_full
@200
-  transmission circuit
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@24
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u_simple_uart.u_uart.txcpu_dbg_st[31:0]
u_simple_uart.u_uart.tx_dbg_st[31:0]
@22
u_simple_uart.u_uart.txreg[7:0]
80
@28
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u_simple_uart.u_uart.txclk
u_simple_uart.u_uart.txdat
u_simple_uart.u_uart.interr_tx_empty
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@200
-  REMOTE (fake) UART
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u_uart_remota.tx_dbg_st[31:0]
@28
u_uart_remota.outdat
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@24
u_uart_remota.rx_dbg_st[31:0]
@28
u_uart_remota.recv[7:0]
@22
u_uart_remota.recv[7:0]
96
@200
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-    write-back
@28
u_core.wb_muxc[2:0]
u_core.wb_wreg
@22
u_core.wb_a_c[4:0]
u_core.wb_c[31:0]
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[pattern_trace] 1
[pattern_trace] 0