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cMIPS
Commit 1ad34d5e authored by Roberto Hexsel's avatar Roberto Hexsel
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improved driver to LCD display and sundry small fixes

parent 3e7cf10d
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Showing with 4196 additions and 122 deletions
cMIPS/bin/compile.sh
View file @ 1ad34d5e
......@@ -149,8 +149,8 @@ mips-ld -EL -e _start ${memory_map} -I "${include}" --script $c_ld \
-o $elf ${c_start}.o ${c_hndlrs}.o ${c_io}.o $obj || exit 1
mips-objcopy -S -j .text -O binary $elf $bin && \
mips-objcopy -S -j .data -j .rodata -j .rodata1 -j .data1 \
-j .sdata -j .lit8 -j .lit4 -j .sbss -j .bss -j .PT \
mips-objcopy -S -j .data -j .data1 -j .lit8 -j .lit4 -j .sdata \
-j .sbss -j .bss -j .rodata1 -j .rodata -j .PT \
-O binary $elf $dat || exit 1
if [ $names = true ] ; then
......@@ -162,8 +162,8 @@ fi
if [ $? == 0 -a $verbose = true ]; then
mips-objdump -z -D -EL $reg_names --show-raw-insn \
--section .text --section .data \
--section .rodata --section .sdata --section .sbss \
--section .bss --section .PT $elf
--section .sdata --section .sbss \
--section .bss --section .rodata --section .PT $elf
fi
if [ $? == 0 -a $miffile = true ] ; then
......
cMIPS/include/cMIPS.h
View file @ 1ad34d5e
......@@ -35,6 +35,8 @@ extern int readInt(int*);
extern void dumpRAM(void);
extern void cmips_delay(int);
extern void delay_us(int);
extern void delay_ms(int);
// external counter (peripheral)
extern void startCounter(int, int);
......@@ -59,7 +61,8 @@ extern int LCDput(int);
extern void LCDclr(void);
extern void LCDtopLine(void);
extern void LCDbotLine(void);
extern void LCDgotoxy(int, int);
extern void LCDputc(char);
extern void DSP7SEGput(int MSD, int MSdot, int lsd, int lsdot);
extern int KBDget(void);
......
cMIPS/include/cMIPSio.c
View file @ 1ad34d5e
......@@ -232,10 +232,13 @@ int SWget(void) {
#define LCD_write_delay 750/4 // 15us / 20ns
#define LCD_busy 0x80
#define LCD_LINE_TWO 0x40 // RAM address for second line
void LCDinit(void) {
int *IO = (int *)IO_LCD_ADDR;
cmips_delay(LCD_reset_cycles); // wait for LCD controller to reset
cmips_delay(LCD_reset_cycles); // wait 50ms for LCD controller to reset
*IO = 0b00110000; // x30 = wake-up
cmips_delay(LCD_delay_30us);
......@@ -265,11 +268,11 @@ void LCDinit(void) {
*IO = 0b00001111; // x0f displayON/OFF: Off, cur=on, blnk=on
cmips_delay(LCD_oper_delay);
*IO = 0b00000110; // x06 entry mode: blink, noShift, addrs++
cmips_delay(LCD_oper_delay);
*IO = 0b00000001; // x01 clear display -- DELAY=0.6ms
cmips_delay(LCD_clear_delay);
*IO = 0b00000110; // x06 entry mode: blink, noShift, addrs++
cmips_delay(LCD_oper_delay);
}
// check LCD's status register
......@@ -284,13 +287,14 @@ int LCDset(int cmd) {
volatile int s;
*IO = cmd;
cmips_delay(LCD_oper_delay);
s = *IO;
while ( (s & LCD_busy) != 0) { s = *IO; }; // still busy?
return(s);
}
// put a character on the current position
// write a "raw" character on the current position
int LCDput(int c) {
int *IO = (int *)IO_LCD_ADDR;
volatile int s;
......@@ -321,6 +325,32 @@ void LCDbotLine(void) {
*IO = 0b11000000; // xc0 RAMaddrs=40, cursor at home on BOTTOM LINE
cmips_delay(LCD_clear_delay);
}
// set cursor at position (x,y)
void LCDgotoxy(int x, int y) {
int address;
if(y != 1)
address = LCD_LINE_TWO;
else
address = 0;
address += (x - 1);
LCDset( 0x80 | (address & 0x7f) ); // write to control register
}
// write a "cooked" character to the display
void LCDputc(char c) {
switch (c) {
case '\f' : LCDset(1); cmips_delay(LCD_clear_delay); break;
case '\n' : LCDgotoxy(1,2); break;
case '\b' : LCDset(0x10); break;
default : LCDput(c); break;
}
}
//-----------------------------------------------------------------------
......@@ -379,4 +409,3 @@ int readCounter(void) {
}; //--------------------------------------------------------------------
cMIPS/include/handlers.s
View file @ 1ad34d5e
......@@ -5,8 +5,7 @@
.set noat # do not use register $1 as $at
.align 2
.set M_StatusIEn,0x0000ff13 # STATUS.intEn=1, user mode, EXL=1
# 0xff13 = -237
.set M_StatusIEn,0x0000ff11 # STATUS.intEn=1, user mode, EXL=0
#================================================================
# interrupt handler for external counter attached to IP5=HW3
......@@ -146,10 +145,10 @@ UARTret:
.equ num_cycles, 64
.global countCompare
.ent countCompare
countCompare:
mfc0 $k1,c0_count # read COMPARE and clear IRQ
countCompare:
mfc0 $k1,c0_count # read COUNT
addiu $k1,$k1,num_cycles # set next interrupt in so many ticks
mtc0 $k1,c0_compare
mtc0 $k1,c0_compare # write to COMPARE to clear IRQ
mfc0 $k0, c0_status # Read STATUS register
ori $k0, $k0, M_StatusIEn # but do not modify its contents
......@@ -241,11 +240,11 @@ disableInterr:
#================================================================
## TLB handlers
## page table entry is { EntryLo0 int0 EntryLo1 int1 }
## page table entry is { EntryLo0, int0, EntryLo1, int1 }
## int{0,1} is
## { fill_31..6, Modified_5, Used_4, Writable_3, eXecutable_2,
## Status_10 },
## Status is 00=unmapped, 01=mapped, 10=secondary_storage
## Status: 00=unmapped, 01=mapped, 10=secondary_storage, 11=panic
#================================================================
......@@ -356,8 +355,6 @@ M_sec_mem: # print message and abort simulation
# (a) fix the fault by (re)loading the mapping into TLB[4];
# (b) check permissions in PT entry and (maybe) kill the process.
#
.global _excp_saves
.global _excp_0180ret
.global handle_TLBL
.global _PT
.set MIDDLE_RAM, (x_DATA_BASE_ADDR + (x_DATA_MEM_SZ/2))
......@@ -438,8 +435,6 @@ L_ret: lw $a0, 9*4($k1) # nothing else to do, return
# returns 0 if V_addr purged, 1 if V_addr not in TLB (probe failure)
#
.text
.global TLB_purge
.set noreorder
.ent TLB_purge
TLB_purge:
......@@ -482,8 +477,9 @@ pu_miss: jr $ra
# delays processing by approx 4*$a0 processor cycles
.text
.set noreorder
.global cmips_delay
.global cmips_delay, delay_cycle, delay_us, delay_ms
.ent cmips_delay
delay_cycle:
cmips_delay:
addiu $a0, $a0, -1
nop
......@@ -494,6 +490,52 @@ cmips_delay:
.end cmips_delay
#----------------------------------------------------------------
#================================================================
# delays processing by $a0 times 1 microsecond
# loop takes 4 cycles = 80ns @ 50MHz
# 1.000ns / 80 = 12.5
# multiply by 2 (sll), add 1, multiply by 12, divide by 2 (sra)
.text
.set noreorder
.ent delay_us
delay_us:
sll $a0, $a0, 1
addiu $a0, $a0, 1
li $v0, 12
mult $v0, $a0
nop
mflo $a0
sra $a0, $a0, 1
_d_us: addiu $a0, $a0, -1
nop
bne $a0, $zero, _d_us
nop
jr $ra
nop
.end delay_us
#----------------------------------------------------------------
#================================================================
# delays processing by $a0 times 1 msecond
# loop takes 4 cycles = 80ns @ 50MHz
# 1.000.000ns / 80 = 12500
.text
.set noreorder
.ent delay_ms
delay_ms:
li $v0, 12500
mult $v0, $a0
nop
mflo $a0
_d_ms: addiu $a0, $a0, -1
nop
bne $a0, $zero, _d_ms
nop
jr $ra
nop
.end delay_ms
#----------------------------------------------------------------
#================================================================
# print a message from within "the kernel"
......
cMIPS/include/start.s
View file @ 1ad34d5e
......@@ -202,6 +202,7 @@ _excp_0100:
## area to save up to 16 registers
.bss
.align 2
.global _excp_saves, _excp_0180ret
.comm _excp_saves 16*4
# _excp_saves[0]=CAUSE, [1]=STATUS, [2]=ASID,
# [8]=$ra, [9]=$a0, [10]=$a1, [11]=$a2, [12]=$a3
......@@ -209,7 +210,7 @@ _excp_0100:
.text
.set noreorder
.set noat
.global _excp_saves, _excp_0180ret
.global _excp_0180ret
.global handle_Mod, handle_TLBL, handle_TLBS
.org x_EXCEPTION_0180,0 # exception vector_180
......@@ -223,10 +224,11 @@ _excp_0180:
sw $k0, 0*4($k1)
andi $k0, $k0, 0x3f # keep only the first 16 ExceptionCodes & b"00"
sll $k0, $k0, 1 # displacement in vector is 8 bytes
sll $k0, $k0, 1 # displacement in vector with 8 bytes/element
lui $k1, %hi(excp_tbl)
ori $k1, $k1, %lo(excp_tbl)
add $k1, $k1, $k0
nop
jr $k1
nop
......@@ -251,32 +253,23 @@ excp_tbl: # see Table 8-25, pg 95,96
nop
wait 0x07 # 7 DBE addr error -- abort simulation
nop
j h_syscall # 8
wait 0x08 # j h_syscall # 8 -- abort simulation
nop
j h_breakpoint # 9
wait 0x09 # j h_breakpoint # 9 -- abort simulation
nop
j h_RI # 10 reserved instruction
wait 0x0a # j h_RI # 10 reserved instruction -- abort simulation
nop
j h_CpU # 11 coprocessor unusable
wait 0x0b # j h_CpU # 11 coprocessor unusable -- abort simulation
nop
j h_Ov # 12 overflow
wait 0x0c # j h_Ov # 12 overflow -- abort simulation
nop
wait 0x0d # 13 trap -- abort simulation
nop
wait 0x0e # reserved, should never get here -- abort simulation
nop
wait 0x0f # FP exception, should never get here -- abort simulation
nop
h_TLBS:
h_syscall:
h_breakpoint:
......@@ -288,10 +281,9 @@ _excp_0180ret:
lui $k1, %hi(_excp_saves) # Read previous contents of STATUS
ori $k1, $k1, %lo(_excp_saves)
lw $k0, 1*4($k1)
# mfc0 $k0, c0_status
# and do not modify its contents
ori $k0, $k0, M_StatusIEn # and keeping user/kernel mode
mtc0 $k0, c0_status # -239 = 0xffff.ff11
ori $k0, $k0, M_StatusIEn # and keep user/kernel mode
mtc0 $k0, c0_status # but enable all interrupts
eret # Return from exception
.end _excp_0180
......@@ -307,7 +299,7 @@ _excp_0180ret:
.extern extCounter # IRQ5 - hwIRQ3, see vhdl/tb_cMIPS.vhd
.set M_CauseIM,0x0000ff00 # keep bits 15..8 -> IM = IP
.set M_StatusIEn,0xff11 # user mode, enable all interrupts
.set M_StatusIEn,0xff11 # user mode, enable all interrupts, EXL=0
.set noreorder
......@@ -323,6 +315,7 @@ _excp_0200:
lui $k1, %hi(handlers_tbl) # plus displacement in j-table of 8 bytes
ori $k1, $k1, %lo(handlers_tbl)
add $k1, $k1, $k0
nop
jr $k1
nop
......@@ -356,8 +349,8 @@ dismiss: # No pending request, must have been noise
_excp_0200ret:
mfc0 $k0, c0_status # Read STATUS register
ori $k0, $k0, M_StatusIEn # except for re-enabling interrupts
mtc0 $k0, c0_status # as it was on interrupt entry
ori $k0, $k0, M_StatusIEn # and re-enable interrupts
mtc0 $k0, c0_status # else keep as it was on int entry
eret # Return from interrupt
nop
......
cMIPS/include/syn_start.s
View file @ 1ad34d5e
......@@ -9,8 +9,7 @@
.set noreorder
.align 2
.extern main
.global _start,_exit,exit
.global _excp_0000, _excp_0100, _excp_0180, _excp_0200, _excp_BFC0
.global _start, _exit, exit
.set MMU_WIRED, 2 ### do not change mapping for base of ROM, I/O
......@@ -62,8 +61,8 @@ _start: nop
mtc0 $k0, cop0_Wired
# initialize SP at top of RAM: ramTop - 16
li $sp, ((x_DATA_BASE_ADDR+x_DATA_MEM_SZ) - 16)
# initialize SP at top of RAM: RAM[1] - 16
li $sp, ((x_DATA_BASE_ADDR + (2*4096)) - 16)
# set STATUS, cop0, hw interrupt IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, 0x1000e011
......@@ -81,16 +80,36 @@ _exit: la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x0311 # display .1.1
sw $k1, 0($k0) # write to 7 segment display
j exit # wait forever
hexit: j hexit # wait forever
nop
.end _start
##
##================================================================
## area to save up to 16 registers
.data
.align 2
.global _excp_saves
.comm _excp_saves 16*4
##===============================================================
## Page Table (empty for synthesis, address must be declared)
##
## .section .PT,"aw",@progbits, .org (x_DATA_BASE_ADDR+2*4096)
## .align 4
.global _PT
.comm _PT 4
##
##================================================================
## exception vector_0000 TLBrefill
##
.org x_EXCEPTION_0000,0
.text
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x0399 # display .9.9
......@@ -125,6 +144,18 @@ _excp_0180:
h0180: j h0180 # wait forever
nop
##
##================================================================
## exception return address (should never get here)
##
.global _excp_0180ret
_excp_0180ret:
la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x0344 # display .4.4
sw $k1, 0($k0) # write to 7 segment display
heret: j heret # wait forever
nop
##
##===============================================================
......@@ -152,7 +183,8 @@ hBFC0: j hBFC0 # wait forever
nop
##================================================================
##
##===============================================================
## main(), normal code starts below -- do not edit next line
......
cMIPS/tests/counter.s
View file @ 1ad34d5e
##
## test if CP0 register COUNT counts monotonically and
## if interrupts are generated when COUNT == COMPARE
##
# Testing the internal counter is difficult because it counts clock cycles
# rather than instructions -- if the I/O or memory latencies change then
# the simulation output also changes and comparisons are impossible.
......@@ -70,8 +75,8 @@ _excp_180:
# interrupt handler ------------------------------------------------
#
.org x_EXCEPTION_0200,0
_excp_200:
mfc0 $k1, cop0_COUNT # read current COUNT
_excp_200:
mfc0 $k1, c0_count # read current COUNT
#sw $k1, 0($15)
addi $22, $22, numCy # interval elapsed?
#sw $22, 0($15) # show old+numCycles
......@@ -80,7 +85,7 @@ _excp_200:
nop
addiu $k1, $k1, numCy # interrupt again in numCy cycles
mtc0 $k1, cop0_COMPARE
mtc0 $k1, c0_compare # write to COMPARE clears the interrupt
#sw $k1, 0($15) # show new limit
li $30, 'i'
......@@ -97,9 +102,6 @@ _excp_200:
and $k0, $k0, $k1
sw $k0, 0($15) # print CAUSE
li $k0, 0x1800ff03 # enable interrupts, EXL=1
mtc0 $k0, c0_status
ehb
eret
err3:
......@@ -118,7 +120,9 @@ err3:
sw $13, x_IO_ADDR_RANGE($15) # blank line
sw $22, 0($15)
li $k0, 0x1800ff02 # disable interrupts, EXL=1
mfc0 $k0, c0_status
li $k1, 0xffff00fe # disable interrupts
and $k0, $k0, $k1
mtc0 $k0, c0_status
ehb
eret
......@@ -148,7 +152,7 @@ main: la $15, x_IO_BASE_ADDR
li $13, '\n'
addiu $5,$zero, numCy # interrupt again in numCy cycles
mtc0 $5,cop0_COMPARE
mtc0 $5,c0_compare
# enable Counter
mfc0 $5,c0_cause
......@@ -163,10 +167,10 @@ main: la $15, x_IO_BASE_ADDR
addiu $11,$12,1 # this is a NOP
#
# check if counting increases monotolically
# check if counting increases monotonically
#
here: addiu $11, $12, 2 # this is a NOP
mfc0 $16, cop0_COUNT # read current COUNT
mfc0 $16, c0_count # read current COUNT
#sw $16, 0($15) # print current COUNT
slt $1, $21, $16 # old < new?
beq $1, $zero, err1 # no, stop simulation
......@@ -190,13 +194,13 @@ there: sw $13, x_IO_ADDR_RANGE($15) # print a newline
or $5, $5, $6
mtc0 $5, c0_cause # disable counter
addiu $11,$12,6 # this is a NOP
mfc0 $18, cop0_COUNT # print current COUNT
mfc0 $18, c0_count # print current COUNT
#sw $18, 0($15)
addiu $11,$12,7 # this is a NOP
addiu $11,$12,8 # this is a NOP
addiu $11,$12,9 # this is a NOP
addiu $11,$12,10 # this is a NOP
mfc0 $19, cop0_COUNT # print current COUNT
mfc0 $19, c0_count # print current COUNT
#sw $19, 0($15)
bne $18, $19, err2 # did counter stop?
nop
......@@ -245,3 +249,4 @@ err2: li $30, 'n'
sw $30, x_IO_ADDR_RANGE($15)
j exit
sw $13, x_IO_ADDR_RANGE($15) # print a newline
cMIPS/tests/mac_kbd_lcd.c
View file @ 1ad34d5e
......@@ -5,9 +5,9 @@
//
int main(void) {
int i;
volatile int state;
int c, k, s;
int i, j;
volatile int state, k;
int c, s;
LCDinit();
......@@ -29,19 +29,34 @@ int main(void) {
LCDbotLine();
j = 0;
while ( 1 == 1 ) {
while( (k = KBDget()) == -1 ) {}; // wait for key
DSP7SEGput(k, 1, 0, 0);
switch(k) {
case 10:
i = '*'; break;
case 11:
i = '#'; break;
case 15:
i = '0'; break;
default:
i = k + 0x30;
}
LCDput(k + 0x30);
// LCDput(0x20);
LCDput(i);
LCDput(0x20);
cmips_delay(12500000);
j = j + 1;
DSP7SEGput(0, 0, k, 1);
if (j == 5) {
j = 0;
LCDgotoxy(1, 0);
}
delay_ms(500);
}
......
cMIPS/tests/mac_lcd.s
View file @ 1ad34d5e
......@@ -378,3 +378,11 @@ delay: addiu $4, $4, -1
#
# string: .asciiz "Hello world! said cMIPS"
#
.bss
nil1: .space 4
.sbss
.data
nil3: .word 0
.sdata
nil4: .word 0
cMIPS/vhdl/core.vhd
View file @ 1ad34d5e
......@@ -109,8 +109,8 @@ architecture rtl of core is
MM_tlb_exception: out boolean;
EX_tlb_stage_MM: in boolean;
MM_tlb_stage_MM: out boolean;
EX_int_req: in reg8;
MM_int_req: out reg8;
EX_int_req: in reg6;
MM_int_req: out reg6;
EX_is_SC: in boolean;
MM_is_SC: out boolean;
EX_is_MFC0: in boolean;
......@@ -147,7 +147,7 @@ architecture rtl of core is
signal ll_sc_bit, MM_LLbit,WB_LLbit: std_logic;
signal LL_update, LL_SC_abort, LL_SC_differ: std_logic;
signal EX_trapped, MM_trapped, EX_ovfl, trap_taken: boolean;
signal int_req, MM_int_req: reg8;
signal int_req, MM_int_req: reg6;
signal can_trap,EX_can_trap : reg2;
signal is_trap, tr_signed, tr_stall: std_logic;
signal tr_is_equal, tr_less_than: std_logic;
......@@ -1018,7 +1018,7 @@ begin
rt_stall := FALSE;
elsif MM_is_SC then
eq_fwd_B <= x"00000000";
rs_stall := FALSE;
rt_stall := FALSE;
else
eq_fwd_B <= MM_result;
rt_stall := FALSE;
......@@ -1787,17 +1787,16 @@ begin
is_nmi <= ( (nmi = '1') and (STATUS(STATUS_ERL) = '0') );
int_req(7) <= (irq(5) or count_eq_compare);
int_req(6) <= irq(4);
int_req(5) <= irq(3);
int_req(4) <= irq(2);
int_req(3) <= irq(1);
int_req(2) <= irq(0);
int_req(1) <= CAUSE(CAUSE_IP1);
int_req(0) <= CAUSE(CAUSE_IP0);
int_req(5) <= (irq(5) or count_eq_compare);
int_req(4) <= irq(4);
int_req(3) <= irq(3);
int_req(2) <= irq(2);
int_req(1) <= irq(1);
int_req(0) <= irq(0);
interrupt <= int_req(7) or int_req(6) or int_req(5) or int_req(4) or
int_req(3) or int_req(2) or int_req(1) or int_req(0);
interrupt <= int_req(5) or int_req(4) or int_req(3) or int_req(3) or
int_req(1) or int_req(0) or
CAUSE(CAUSE_IP1) or CAUSE(CAUSE_IP0);
is_interr <= ( (interrupt = '1') and
(STATUS(STATUS_EXL) = '0') and
......@@ -2338,12 +2337,12 @@ begin
newCAUSE(CAUSE_IV) := CAUSE(CAUSE_IV);
newCAUSE(CAUSE_WP) := '0';
newCAUSE(21 downto 16) := b"000000";
newCAUSE(CAUSE_IP7) := MM_int_req(7);
newCAUSE(CAUSE_IP6) := MM_int_req(6);
newCAUSE(CAUSE_IP5) := MM_int_req(5);
newCAUSE(CAUSE_IP4) := MM_int_req(4);
newCAUSE(CAUSE_IP3) := MM_int_req(3);
newCAUSE(CAUSE_IP2) := MM_int_req(2);
newCAUSE(CAUSE_IP7) := MM_int_req(5);
newCAUSE(CAUSE_IP6) := MM_int_req(4);
newCAUSE(CAUSE_IP5) := MM_int_req(3);
newCAUSE(CAUSE_IP4) := MM_int_req(2);
newCAUSE(CAUSE_IP3) := MM_int_req(1);
newCAUSE(CAUSE_IP2) := MM_int_req(0);
newCAUSE(CAUSE_IP1) := CAUSE(CAUSE_IP1);
newCAUSE(CAUSE_IP0) := CAUSE(CAUSE_IP0);
newCAUSE(7) := '0';
......
cMIPS/vhdl/exception.vhd
View file @ 1ad34d5e
......@@ -139,8 +139,8 @@ entity reg_excp_EX_MM is
MM_tlb_exception: out boolean;
EX_tlb_stage_mm: in boolean;
MM_tlb_stage_mm: out boolean;
EX_int_req: in reg8;
MM_int_req: out reg8;
EX_int_req: in reg6;
MM_int_req: out reg6;
EX_is_SC: in boolean;
MM_is_SC: out boolean;
EX_is_MFC0: in boolean;
......
cMIPS/vhdl/incomplete/DHW.mif 0 → 100644
View file @ 1ad34d5e
This diff is collapsed.
cMIPS/vhdl/incomplete/memoriavideo.qip 0 → 100644
View file @ 1ad34d5e
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "memoriavideo.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "memoriavideo_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "memoriavideo.cmp"]
cMIPS/vhdl/incomplete/memoriavideo.vhd 0 → 100644
View file @ 1ad34d5e
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: memoriavideo.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 177 11/07/2012 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY memoriavideo IS
PORT
(
address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END memoriavideo;
ARCHITECTURE SYN OF memoriavideo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;