Commit 1ffcdd18 authored by Roberto Hexsel's avatar Roberto Hexsel

2nd version for SDcard controller; changed names for CP0 register in assembly test programs

parent 11c1bf18
......@@ -10,18 +10,19 @@
#define x_IO_ADDR_MASK (0 - x_IO_ADDR_RANGE)
#define IO_PRINT_ADDR x_IO_BASE_ADDR;
#define IO_STDOUT_ADDR (x_IO_BASE_ADDR + 1 * x_IO_ADDR_RANGE);
#define IO_STDIN_ADDR (x_IO_BASE_ADDR + 2 * x_IO_ADDR_RANGE);
#define IO_READ_ADDR (x_IO_BASE_ADDR + 3 * x_IO_ADDR_RANGE);
#define IO_WRITE_ADDR (x_IO_BASE_ADDR + 4 * x_IO_ADDR_RANGE);
#define IO_COUNT_ADDR (x_IO_BASE_ADDR + 5 * x_IO_ADDR_RANGE);
#define IO_FPU_ADDR (x_IO_BASE_ADDR + 6 * x_IO_ADDR_RANGE);
#define IO_UART_ADDR (x_IO_BASE_ADDR + 7 * x_IO_ADDR_RANGE);
#define IO_STATS_ADDR (x_IO_BASE_ADDR + 8 * x_IO_ADDR_RANGE);
#define IO_DSP7SEG_ADDR (x_IO_BASE_ADDR + 9 * x_IO_ADDR_RANGE);
#define IO_KEYBD_ADDR (x_IO_BASE_ADDR +10 * x_IO_ADDR_RANGE);
#define IO_LCD_ADDR (x_IO_BASE_ADDR +11 * x_IO_ADDR_RANGE);
#define IO_PRINT_ADDR x_IO_BASE_ADDR
#define IO_STDOUT_ADDR (x_IO_BASE_ADDR + 1 * x_IO_ADDR_RANGE)
#define IO_STDIN_ADDR (x_IO_BASE_ADDR + 2 * x_IO_ADDR_RANGE)
#define IO_READ_ADDR (x_IO_BASE_ADDR + 3 * x_IO_ADDR_RANGE)
#define IO_WRITE_ADDR (x_IO_BASE_ADDR + 4 * x_IO_ADDR_RANGE)
#define IO_COUNT_ADDR (x_IO_BASE_ADDR + 5 * x_IO_ADDR_RANGE)
#define IO_FPU_ADDR (x_IO_BASE_ADDR + 6 * x_IO_ADDR_RANGE)
#define IO_UART_ADDR (x_IO_BASE_ADDR + 7 * x_IO_ADDR_RANGE)
#define IO_STATS_ADDR (x_IO_BASE_ADDR + 8 * x_IO_ADDR_RANGE)
#define IO_DSP7SEG_ADDR (x_IO_BASE_ADDR + 9 * x_IO_ADDR_RANGE)
#define IO_KEYBD_ADDR (x_IO_BASE_ADDR +10 * x_IO_ADDR_RANGE)
#define IO_LCD_ADDR (x_IO_BASE_ADDR +11 * x_IO_ADDR_RANGE)
#define IO_SDCARD_ADDR (x_IO_BASE_ADDR +12 * x_IO_ADDR_RANGE)
extern void exit(int);
......@@ -42,6 +43,8 @@ extern void writeClose(void);
extern int readInt(int*);
extern void dumpRAM(void);
extern int print_sp(void);
extern int print_status(void);
extern int print_cause(void);
extern char *memcpy(char*, const char*, int);
extern char *memset(char*, const int, int);
......
......@@ -19,6 +19,7 @@
.set HW_dsp7seg_addr,(x_IO_BASE_ADDR + 9 * x_IO_ADDR_RANGE)
.set HW_keybd_addr, (x_IO_BASE_ADDR + 10 * x_IO_ADDR_RANGE)
.set HW_lcd_addr, (x_IO_BASE_ADDR + 11 * x_IO_ADDR_RANGE)
.set HW_SDcard_addr, (x_IO_BASE_ADDR + 12 * x_IO_ADDR_RANGE)
# see vhdl/packageMemory.vhd for addresses
.set x_EXCEPTION_0000,0x00000130
......@@ -28,25 +29,6 @@
.set x_EXCEPTION_BFC0,0x000004E0
.set x_ENTRY_POINT, 0x00000500
.set cop0_Index, $0
.set cop0_Random, $1
.set cop0_EntryLo0,$2
.set cop0_EntryLo1,$3
.set cop0_Context ,$4
.set cop0_PageMask,$5
.set cop0_Wired, $6
.set cop0_BadVAddr,$8
.set cop0_COUNT ,$9
.set cop0_EntryHi ,$10
.set cop0_COMPARE ,$11
.set cop0_STATUS ,$12
.set cop0_CAUSE ,$13
.set cop0_EPC, $14
.set cop0_CONFIG, $16
.set cop0_CONFIG_f0,0
.set cop0_CONFIG_f1,1
.set cop0_LLAddr, $17
.set cop0_ErrorPC, $30
.set c0_index, $0
.set c0_random, $1
......@@ -70,10 +52,17 @@
# reset: COP0 present, at exception level, all else disabled
.set cop0_STATUS_reset,0x10000002
.set c0_status_reset,0x10000002
# normal state: COP0 present, user mode, all IRQs enabled
.set cop0_STATUS_normal,0x1000ff11
.set c0_status_normal,0x1000ff11
# reset: COUNTER stopped, use special interrVector, no interrupts
.set cop0_CAUSE_reset, 0x0880007c
.set c0_cause_reset, 0x0880007c
.equ led_RED, 0x4000
.equ led_GRE, 0x2000
.equ led_BLU, 0x1000
.equ led_OFF, 0x0FFF
......@@ -406,8 +406,8 @@ void LCDbyte(unsigned char n) {
//=======================================================================
// 7 segment display
// rgb values are in [0,7]
// 7 segment display and RGB leds
// rgb values are in [0,7], stored in bits R=bit14, G=bit13, B=bit12
// MSdigit bits bit7..4, lsDigit bit3..0, MSD dot bit9, lsD dot bit8
//=======================================================================
void DSP7SEGput(int MSD, int MSdot, int lsd, int lsdot, int rgb) {
......@@ -420,7 +420,7 @@ void DSP7SEGput(int MSD, int MSdot, int lsd, int lsdot, int rgb) {
dig1 = (MSD & 0xf) << 4;
dig0 = (lsd & 0xf);
leds = (rgb & 0x07) <<10;
leds = (rgb & 0x07) <<12;
*IO = leds | dot1 | dot0 | dig1 | dig0;
}
......
......@@ -534,6 +534,34 @@ _d_ms: addiu $a0, $a0, -1
nop
.end delay_ms
#----------------------------------------------------------------
##
## read contents of control registers (for debugging)
##
.global print_sp, print_status, print_cause
.ent print_sp
print_sp:
jr $ra
move $v0, $sp
.end print_sp
.ent print_status
print_status:
mfc0 $v0, c0_status
nop
jr $ra
nop
.end print_status
.ent print_cause
print_cause:
mfc0 $v0, c0_cause
nop
jr $ra
nop
.end print_cause
#----------------------------------------------------------------
#================================================================
......
......@@ -131,8 +131,8 @@ _start:
la $sp, (MIDDLE_RAM - 16)
# set STATUS, cop0, hw interrupts IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, cop0_STATUS_normal
# set STATUS, c0, hw interrupts IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, c0_status_normal
mtc0 $k0, c0_status
......@@ -410,8 +410,6 @@ PT_update:
##===============================================================
## Page Table
##
......
......@@ -25,11 +25,11 @@ _start: nop
# needed so systems without a page table will not break
# read TLB[4] and write it to TLB[2]
li $k0, 4
mtc0 $k0, cop0_Index
mtc0 $k0, c0_index
ehb
tlbr
li $k1, 2
mtc0 $k1, cop0_Index
mtc0 $k1, c0_index
ehb
tlbwi
......@@ -37,28 +37,28 @@ _start: nop
# then set another mapping onto TLB[4], to avoid replicated entries
li $a0, ( (x_DATA_BASE_ADDR + 8*4096) >>12 )
sll $a2, $a0, 12 # tag for RAM[8,9] double-page
mtc0 $a2, cop0_EntryHi
mtc0 $a2, c0_entryhi
li $a0, ((x_DATA_BASE_ADDR + 8*4096) >>12 )
sll $a1, $a0, 6 # RAM[8] (even)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo0
mtc0 $a1, c0_entrylo0
li $a0, ( (x_DATA_BASE_ADDR + 9*4096) >>12 )
sll $a1, $a0, 6 # RAM[9] (odd)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo1
mtc0 $a1, c0_entrylo1
# and write it to TLB[4]
li $k0, 4
mtc0 $k0, cop0_Index
mtc0 $k0, c0_index
tlbwi
# pin down first four TLB entries: ROM[0], RAM[0], stack and I/O
li $k0, 4
mtc0 $k0, cop0_Wired
mtc0 $k0, c0_wired
# initialize SP at top of RAM: RAM[1] - 16
......@@ -66,7 +66,7 @@ _start: nop
# set STATUS, cop0, hw interrupt IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, 0x1000e011
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
j main
nop
......@@ -78,21 +78,41 @@ exit:
_exit: la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x1300 # display .0.0, RED led
sw $k1, 0($k0) # write to 7 segment display
li $k0, 0x10000010
mtc0 $k0, c0_status # disable interrupts
nop
hexit: j hexit # wait forever
nop
.end _start
##
## read contants of the stack-pointer (for debugging)
## read contents of control registers (for debugging)
##
.global print_sp
.global print_sp, print_status, print_cause
.ent print_sp
print_sp:
jr $ra
move $v0, $sp
.end print_sp
.ent print_status
print_status:
mfc0 $v0, c0_status
nop
jr $ra
nop
.end print_status
.ent print_cause
print_cause:
mfc0 $v0, c0_cause
nop
jr $ra
nop
.end print_cause
##
##================================================================
......
......@@ -10,7 +10,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
j main
nop
......@@ -32,7 +32,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -42,7 +42,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -80,7 +80,7 @@ excp_180:
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......
......@@ -9,7 +9,7 @@ _start: nop
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, cop0_STATUS_normal
li $k0, c0_status_normal
mtc0 $k0, c0_status
j main
......@@ -33,7 +33,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -43,7 +43,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -97,7 +97,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......
......@@ -15,7 +15,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
j main
nop
......@@ -35,7 +35,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -45,7 +45,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -60,13 +60,13 @@ _excp_0100:
.ent _excp_180
excp_180:
_excp_180:
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
sw $k0, 0($15) # print CAUSE
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($15) # print new-line
mfc0 $k1, cop0_EPC # advance EPC to next instruction
mfc0 $k1, c0_epc # advance EPC to next instruction
addi $k1, $k1, 4
mtc0 $k1, cop0_EPC
mtc0 $k1, c0_epc
addiu $7, $7, -1
eret
.end _excp_180
......@@ -79,7 +79,7 @@ _excp_200:
##
## this exception should not happen
##
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
sw $k0,0($15) # print CAUSE
li $k1, 'e'
sw $k1, x_IO_ADDR_RANGE($15)
......@@ -95,7 +95,7 @@ _excp_200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......
......@@ -13,7 +13,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
j main
nop
......@@ -37,7 +37,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -47,7 +47,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -64,14 +64,14 @@ _excp_0100:
excp_180:
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
# andi $k0, $k0, 0x003f # mask off cause of exception
sw $k0, 0($14) # print CAUSE
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
li $k0, 0x10000010 # clear status of exception
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
j apocalipse # and print a message
nop
......@@ -83,7 +83,7 @@ excp_180:
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -94,7 +94,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -119,19 +119,19 @@ main: la $14, x_IO_BASE_ADDR # used by handler
# sw $2, 0($14)
li $8, (ram_displ & 0xfffff000) # keep VPN2
mtc0 $8, cop0_EntryHi
mtc0 $8, c0_entryhi
# sw $8, 0($14)
li $6, ( ((ram_displ >>12) <<6) | 0b000111 ) # PPN0
mtc0 $6, cop0_EntryLo0
mtc0 $6, c0_entrylo0
# sw $6, 0($14)
li $7, ( (((ram_displ+4096) >>12) <<6) | 0b000111 ) # PPN1
mtc0 $7, cop0_EntryLo1
mtc0 $7, c0_entrylo1
# sw $7, 0($14)
li $5, 7 # read TLB(7)
mtc0 $5, cop0_Index
mtc0 $5, c0_index
ehb
tlbwi
......
......@@ -18,7 +18,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
.set bad_address, (x_INST_BASE_ADDR + x_INST_MEM_SZ + 4096)
......@@ -27,21 +27,21 @@ _start: nop
li $a0, ( bad_address >>12 )
sll $a2, $a0, 12 # tag for RAM[8,9] double-page
mtc0 $a2, cop0_EntryHi
mtc0 $a2, c0_entryhi
li $a0, ((bad_address + 0*4096) >>12 )
sll $a1, $a0, 6 # ROM_top+4096 (even)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo0
mtc0 $a1, c0_entrylo0
li $a0, ((bad_address + 1*4096) >>12 )
sll $a1, $a0, 6 # ROM_top+8192 (odd)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
mtc0 $a1, cop0_EntryLo1
mtc0 $a1, c0_entrylo1
# and write it to TLB[3]
li $k0, 3
mtc0 $k0, cop0_Index
mtc0 $k0, c0_index
tlbwi
j main
......@@ -66,7 +66,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -76,7 +76,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -93,13 +93,13 @@ _excp_0100:
excp_180:
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
sw $k0, 0($14) # print CAUSE
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
li $k0, 0x10000010 # clear status of exception
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
j apocalipse # and print a message
nop
......@@ -110,7 +110,7 @@ excp_180:
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......@@ -121,7 +121,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
......
......@@ -17,12 +17,12 @@
.global _exit
_start: nop
li $k0, cop0_STATUS_reset # RESET, kernel mode, all else disabled
li $k0, c0_status_reset # RESET, kernel mode, all else disabled
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x1800ff01 # RESET_STATUS, kernel mode, interr enabled
mtc0 $k0, c0_status
li $k0, cop0_CAUSE_reset # RESET, disable counter
li $k0, c0_cause_reset # RESET, disable counter
mtc0 $k0, c0_cause
la $15,x_IO_BASE_ADDR
......
......@@ -8,12 +8,12 @@
.ent _start
_start: nop
li $k0,0x10000002 # RESET_STATUS, kernel mode, all else disabled
mtc0 $k0,cop0_STATUS
mtc0 $k0,c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: memTop-8
li $k0,0x00000000 # nothing happens
mtc0 $k0,cop0_CAUSE
mtc0 $k0,c0_cause
li $k0, 0x1000ff01 # enable interrupts
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
nop
jal main
exit:
......@@ -32,12 +32,12 @@ _exit: nop # flush pipeline
.global excp_180
.ent excp_180
excp_180:
mfc0 $k0, cop0_CAUSE # show cause
mfc0 $k0, c0_cause # show cause
sw $k0, 0($15)
li $k1, 0x00000000 # disable SW interrupt
mtc0 $k1, cop0_CAUSE
mtc0 $k1, c0_cause
li $k0, 0x1000ff00 # disable interrupts
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
eret
.end excp_180
......
......@@ -15,6 +15,7 @@
#define SEQ_SZ 10
/*---------------------------------------------------------------------------*/
void fib(unsigned int* buf, unsigned int n) {
......@@ -45,7 +46,7 @@ void myprint(unsigned int* buf, unsigned int n) {
/*---------------------------------------------------------------------------*/
int main() {
unsigned int buf[10];
unsigned int buf[SEQ_SZ];
fib(buf, SEQ_SZ);
myprint(buf, SEQ_SZ);
......
......@@ -8,10 +8,10 @@
.ent _start
_start: nop
li $k0, 0x18000002 # RESET_STATUS, kernel mode, all else disabled
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE, no exceptions
mtc0 $k0, cop0_CAUSE # clear CAUSE
mtc0 $k0, c0_cause # clear CAUSE
nop
jal main
......@@ -33,19 +33,19 @@ _exit: nop # flush pipeline
.ent _excp_180
excp_180:
_excp_180:
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
sw $k0,0($14) # print CAUSE
mfc0 $k0, cop0_EPC #
mfc0 $k0, c0_epc #
sw $k0,0($14) # print EPC
addiu $7,$7,-1
addiu $15,$15,-1 # fix the invalid address
li $k0, 0x18000300 # disable interrupts
mtc0 $k0, cop0_STATUS
mfc0 $k0, cop0_EPC # fix the return address
mtc0 $k0, c0_status
mfc0 $k0, c0_epc # fix the return address
srl $k0,$k0,2
sll $k0,$k0,2
mtc0 $k0, cop0_EPC
mtc0 $zero, cop0_CAUSE # clear CAUSE
mtc0 $k0, c0_epc
mtc0 $zero, c0_cause # clear CAUSE
eret
.end _excp_180
......
......@@ -8,12 +8,12 @@
.ent _start
_start: nop
li $k0,0x10000002 # RESET_STATUS, kernel mode, all else disabled
mtc0 $k0,cop0_STATUS
mtc0 $k0,c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: memTop-8
li $k0,0x00000000 # nothing happens
mtc0 $k0,cop0_CAUSE
mtc0 $k0,c0_cause
li $k0, 0x1000ff01 # enable interrupts
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
nop
jal main
exit:
......@@ -32,12 +32,12 @@ _exit: nop # flush pipeline
.global excp_180
.ent excp_180
excp_180:
mfc0 $k0, cop0_CAUSE # show cause
mfc0 $k0, c0_cause # show cause
sw $k0, 0($15)
li $k1, 0x00000000 # disable SW interrupt
mtc0 $k1, cop0_CAUSE
mtc0 $k1, c0_cause
li $k0, 0x1000ff00 # disable interrupts
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
eret
.end excp_180
......
......@@ -12,12 +12,12 @@
.global _exit
_start: nop
li $k0, cop0_STATUS_reset # RESET, kernel mode, all else disabled
li $k0, c0_status_reset # RESET, kernel mode, all else disabled
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x1000ff01 # RESET_STATUS, kernel mode, interr enabled
mtc0 $k0, c0_status
li $k0, cop0_CAUSE_reset # RESET, disable counter
li $k0, c0_cause_reset # RESET, disable counter
mtc0 $k0, c0_cause
la $15,x_IO_BASE_ADDR
......
......@@ -23,12 +23,12 @@
.set ext_restart, 0xc0000000 # start ext_counter, intrr enable
_start: nop
li $k0, cop0_STATUS_reset # RESET, kernel mode, all else disabled
li $k0, c0_status_reset # RESET, kernel mode, all else disabled
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x1000ff01 # RESET_STATUS, kernel mode, interr enabled
mtc0 $k0, c0_status
li $k0, cop0_CAUSE_reset # RESET, disable counter
li $k0, c0_cause_reset # RESET, disable counter
mtc0 $k0, c0_cause
la $15,x_IO_BASE_ADDR
......
......@@ -8,10 +8,10 @@
.ent _start
_start: nop
li $k0, 0x18000002 # RESET_STATUS, kernel mode, all else disabled
mtc0 $k0, cop0_STATUS
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE, no exceptions
mtc0 $k0, cop0_CAUSE # clear CAUSE
mtc0 $k0, c0_cause # clear CAUSE
nop
jal main
......@@ -33,19 +33,19 @@ _exit: nop # flush pipeline
.ent _excp_180
excp_180:
_excp_180:
mfc0 $k0, cop0_CAUSE
mfc0 $k0, c0_cause
sw $k0,0($14) # print CAUSE
mfc0 $k0, cop0_EPC #
mfc0 $k0, c0_epc #
sw $k0,0($14) # print EPC
addiu $7,$7,-1
addiu $15,$15,-1 # fix the invalid address
li $k0, 0x18000300 # disable interrupts
mtc0 $k0, cop0_STATUS
mfc0 $k0, cop0_EPC # fix the return address
mtc0 $k0, c0_status
mfc0 $k0, c0_epc # fix the return address
srl $k0,$k0,2
sll $k0,$k0,2
mtc0 $k0, cop0_EPC
mtc0 $zero, cop0_CAUSE # clear CAUSE
mtc0 $k0, c0_epc
mtc0 $zero, c0_cause # clear CAUSE
eret