Commit a26f0c76 authored by Roberto Hexsel's avatar Roberto Hexsel

adding revision 106 from Sourceforge

parents
cMIPS
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.
Processor model runs C code, compiled with GCC;
Testbench includes processor, RAM, ROM and file I/O;
Core has all forwarding paths and is fully interlocked for data and control hazards;
Coprocessor0 is partially implemented, six hardware interrupts + NMI implemented in "Interrupt Compatibility Mode";
The instructions break, syscall, trap, mfc0, mtc0, eret, ei, di, ll, sc are implemented;
Partial-word loads and stores (word, half-word, byte) implemented at the processor's memory interface.
This diff is collapsed.
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 10:43:27 May 27, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "10:43:27 May 27, 2014"
# Revisions
PROJECT_REVISION = "tb_cMIPS"
This diff is collapsed.
## Generated SDC file "tb_cMIPS.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sat Aug 16 21:02:22 2014"
##
## DEVICE "EP4CE30F23C7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 2
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clock_50mhz} -period 20.00 -waveform { 0.00 10.00 } [get_ports {clock_50mhz}]
# create_clock -name clock_50mhz_virt -period 20.00
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks -create_base_clocks
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -clock clock_50mhz -max 3 [all_inputs]
set_input_delay -clock clock_50mhz -min 1 [all_inputs]
#**************************************************************
# Set Output Delay
#**************************************************************
# set_output_delay -clock clock_50mhz 3 [all_outputs]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#set_false_path -from * -to [get_ports {LEDM_C* LEDM_R* LED_B LED_G LED_R}]
#set_false_path -from [get_ports {KEY* SW*}] -to *
#set_false_path -from * -to [get_ports {LCD_BACKLIGHT LCD_D* LCD_EN LCD_RS LCD_RW UART_TXD}]
set_false_path -from * -to [get_ports {led_b led_g led_r}]
set_false_path -from [get_ports {key* sw*}] -to *
set_false_path -from * -to [get_ports {disp1* disp0*}]
set_false_path -from * -to [get_ports {lcd_*}]
set_false_path -from [get_ports {lcd_*}] -to *
set_false_path -from * -to [get_ports {uart_*}]
set_false_path -from [get_ports {uart_*}] -to *
# set_false_path -from [get_ports {reset_n}] -to [all_registers]
# set_false_path -from [get_ports {clock_50mhz}] -to *
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
{ "" "" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "VHDL Process Statement warning at aux.vhd(281): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "VHDL Process Statement warning at aux.vhd(300): inferring latch(es) for signal or variable \"q\", which holds its previous value in one or more paths through the process" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "VHDL Process Statement warning at aux.vhd(251): inferring latch(es) for signal or variable \"Q\", which holds its previous value in one or more paths through the process" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 15610 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 292013 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "308012" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
This diff is collapsed.
#!/bin/bash
# set -x
if [ ! -v tree ] ; then
# you must set the location of the cMIPS root directory in the variable tree
# tree=${HOME}/cMIPS
# export tree="$(dirname "$(pwd)")"
export tree="$(echo $PWD | sed -e 's:\(/.*/cMIPS\)/.*:\1:')"
fi
# path to cross-compiler and binutils must be set to your installation
WORK_PATH=/home/soft/linux/mips/cross/bin
HOME_PATH=/opt/cross/bin
if [ -x /opt/cross/bin/mips-gcc ] ; then
export PATH=$PATH:$HOME_PATH
elif [ -x /home/soft/linux/mips/cross/bin/mips-gcc ] ; then
export PATH=$PATH:$WORK_PATH
else
echo -e "\n\n\tPANIC: cross-compiler not installed\n\n" ; exit 1;
fi
usage() {
cat << EOF
usage: $0 [options] SOURCE.s
creates {prog,data}.bin to be input by textbench
OPTIONS:
-h Show this message
-O n Optimization level, defaults to n=0 {0,1,2,3}
-v Verbose, creates memory map: SOURCE.map
-mif Generate output file ROM.mif for Altera's FPGAs
EOF
}
errorED()
{
cat <<EOF
$pkg_vhd NEWER than header files;
problem running edMemory.sh in $0
EOF
exit 1
}
if [ $# = 0 ] ; then usage ; exit 1 ; fi
miffile=false
verbose=false
unset mem_map
level=0
bin="${tree}"/bin
include="${tree}"/include
srcVHDL="${tree}"/vhdl
c_ld="${include}"/cMIPS.ld
c_s="${include}"/cMIPS.s
while true ; do
case "$1" in
-h) usage ; exit 1
;;
-O) level=$2
shift
;;
-O1) level=1
;;
-O2) level=2
;;
-O3) level=3
;;
-v) verbose=true
;;
-mif) miffile=true
;;
-x) set -x
;;
*) inp=${1%.s}
if [ ${inp}.s != $1 ] ; then
usage ; echo " invalid option: $1"; exit 1 ; fi
break
;;
esac
shift
done
if [ -z $inp ] ; then usage ; exit 1 ; fi
pkg_vhd="${srcVHDL}"/packageMemory.vhd
if [ $pkg_vhd -nt $c_ld -o $pkg_vhd -nt $c_s ] ; then
"${bin}"/edMemory.sh -v || errorED || exit 1
fi
if [ $verbose = true ] ; then mem_map="-Map ${inp}.map" ; fi
asm=${inp}.s
obj=${inp}.o
elf=${inp}.elf
bin=prog.bin
dat=data.bin
(mips-as -O${level} -EL -mips32r2 -I "${include}" -o $obj $asm || exit 1) &&\
mips-ld -EL -e _start ${mem_map} -I "${include}" --script $c_ld -o $elf $obj &&\
mips-objcopy -S -j .text -O binary $elf $bin &&\
mips-objcopy -S -j .data -j .rodata -O binary $elf $dat &&\
chmod a-x $bin $dat &&\
if [ $verbose = true ] ; then
mips-objdump -z -D -EL -M reg-names=numeric --show-raw-insn \
--section .text --section .data --section .rodata --section .bss $elf
fi &&\
if [ $miffile = true ] ; then
elf2mif.sh "$elf" || exit 1
fi
# --section .reginfo
#!/bin/bash
## ------------------------------------------------------------------------
## cMIPS, Roberto Hexsel, 30set2013, rev 08jan2015
## ------------------------------------------------------------------------
# set -x
errorED()
{
cat <<EOF
$pkg_vhd NEWER than header files;
problem running edMemory.sh in $0
EOF
exit 1
}
errorCOMPILING()
{
cat <<EOF
$0: error in compiling VHDL sources
EOF
exit 1
}
if [ ! -v tree ] ; then
# you must set the location of the cMIPS root directory in the variable tree
# tree=${HOME}/cMIPS
# tree=${HOME}/cmips-code/cMIPS
export tree="$(echo $PWD | sed -e 's:^\(/.*/cMIPS\)/.*:\1:')"
fi
bin="${tree}"/bin
include="${tree}"/include
srcVHDL="${tree}"/vhdl
# obj="${tree}"/obj
c_ld="${include}"/cMIPS.ld
c_s="${include}"/cMIPS.s
c_h="${include}"/cMIPS.h
pkg_vhd="$srcVHDL/packageMemory.vhd"
if [ $pkg_vhd -nt $c_ld -o\
$pkg_vhd -nt $c_s -o\
$pkg_vhd -nt $c_h ] ; then
"${bin}"/edMemory.sh -v || errorED || exit 1
fi
# cd "${obj}"
cd "${srcVHDL}"
simulator=tb_cmips
pkg="packageWires.vhd packageMemory.vhd packageExcp.vhd"
src="altera.vhd macnica.vhd aux.vhd memory.vhd cache.vhd instrcache.vhd ram.vhd rom.vhd units.vhd io.vhd uart.vhd pipestages.vhd exception.vhd core.vhd tb_cMIPS.vhd"
# build simulator
#ghdl --clean
#ghdl -a --ieee=standard "${srcVHDL}"/packageWires.vhd || exit 1
#ghdl -a --ieee=standard "${srcVHDL}"/packageMemory.vhd || exit 1
#ghdl -a --ieee=standard "${srcVHDL}"/packageExcp.vhd || exit 1
#for F in ${src} ; do
# if [ ! -s ${F}.o -o "${srcVHDL}"/${F}.vhd -nt ${F}.o ] ; then
# ghdl -a --ieee=standard "${srcVHDL}"/${F}.vhd || exit 1
# fi
#done
#
#ghdl -c "${srcVHDL}"/*.vhd -e ${simulator} || exit 1
# NOTE: when you add a new sourcefile to this project, you must include it
# with "ghdl -i newFile.vhd" so that learns about it. It may be
# a good idea to remove ./.last_import fo force a full rebuild.
# Of course, newFile.vhd must be added to the $src variable.
# if never imported sources, do it now
if [ ! -f .last_import ] ; then
ghdl -i ${pkg}
ghdl -i ${src}
touch .last_import
fi
ghdl -m ${simulator} || errorCOMPILING
mv ${simulator} ..
cd ..
#!/bin/bash
# set -x
if [ ! -v tree ] ; then
# you must set the location of the cMIPS root directory in the variable tree
# tree=${HOME}/cMIPS
# tree=${HOME}/cmips-code/cMIPS
export tree="$(echo $PWD | sed -e 's:^\(/.*/cMIPS\)/.*:\1:')"
fi
# path to cross-compiler and binutils must be set to your installation
WORK_PATH=/home/soft/linux/mips/cross/bin
HOME_PATH=/opt/cross/bin
if [ -x /opt/cross/bin/mips-gcc ] ; then
export PATH=$PATH:$HOME_PATH
elif [ -x /home/soft/linux/mips/cross/bin/mips-gcc ] ; then
export PATH=$PATH:$WORK_PATH
else
echo -e "\n\n\tPANIC: cross-compiler not installed\n\n" ; exit 1;
fi
usage()
{
cat << EOF
usage: $0 [options] source.c
creates {prog,data}.bin to be input by textbench
OPTIONS:
-h Show this message
-O n Optimization level, defaults to n=1 {0,1,2,3}
-v Verbose, creates memory map: source.map
-W GIve -Wall to GCC
-mif Generate output file ROM.mif for Altera's FPGAs
-syn Compile for synthesis, else for simulation
EOF
}
errorED()
{
cat <<EOF
$pkg_vhd NEWER than header files;
problem running edMemory.sh in $0
EOF
exit 1
}
if [ $# = 0 ] ; then usage ; exit 1 ; fi
miffile=false
synth=false
verbose=false
unset memory_map
level=1
while true ; do
case "$1" in
-h) usage ; exit 1
;;
-O) level=$2
shift
;;
-O0) level=0
;;
-O1) level=1
;;
-O2) level=2
;;
-O3) level=3
;;
-W | -Wall) warn=-Wall
;;
-v) verbose=true
;;
-mif) miffile=true
;;
-syn) synth=true
;;
-x) set -x
;;
*) inp=${1%.c}
if [ ${inp}.c != $1 ] ; then
usage ; echo " invalid option: $1"; exit 1 ; fi
break
;;
esac
shift
done
if [ -z $inp ] ; then usage ; exit 1 ; fi
bin="${tree}"/bin
include="${tree}"/include
srcVHDL="${tree}"/vhdl
c_ld="${include}"/cMIPS.ld
c_h="${include}"/cMIPS.h
c_s="${include}"/cMIPS.s
c_io="${include}"/cMIPSio
c_start="${include}"/start
c_hndlrs="${include}"/handlers
c_stop="${include}"/stop
pkg_vhd="${srcVHDL}"/packageMemory.vhd
if [ $pkg_vhd -nt $c_h -o\
$pkg_vhd -nt $c_ld -o\
$pkg_vhd -nt $c_s ] ; then
"${bin}"/edMemory.sh -v || errorED || exit 1
fi
src=${inp}.c
asm=${inp}.s
obj=${inp}.o
elf=${inp}.elf
bin=prog.bin
dat=data.bin
if [ $verbose = true ]; then memory_map="-Map ${inp}.map" ; fi
if [ $synth = true ];
then S="-D FOR_SYNTHESIS" ;
else S="-U FOR_SYNTHESIS" ; fi
(mips-gcc -O${level} $warn -DcMIPS -mno-gpopt -I"${include}" -S ${src} $S\
-o ${asm} || exit 1) && \
mips-gcc -O1 -DcMIPS -mno-gpopt -I"${include}" -S ${c_io}.c -o ${c_io}.s $S &&\
mips-as -O1 -EL -mips32 -I "${include}" -o ${obj} ${asm} && \
mips-as -O1 -EL -mips32 -I "${include}" -o ${c_start}.o ${c_start}.s && \
mips-as -O1 -EL -mips32 -I "${include}" -o ${c_hndlrs}.o ${c_hndlrs}.s && \
mips-as -O1 -EL -mips32 -I "${include}" -o ${c_stop}.o ${c_stop}.s && \
mips-as -O1 -EL -mips32 -I "${include}" -o ${c_io}.o ${c_io}.s && \
mips-ld -EL -e _start ${memory_map} -I "${include}" --script $c_ld \
-o $elf ${c_start}.o ${c_hndlrs}.o ${c_io}.o $obj ${c_stop}.o || exit 1
mips-objcopy -S -j .text -O binary $elf $bin && \
mips-objcopy -S -j .data -j .rodata -j .rodata1 -j .data1 \
-j .sdata -j .lit8 -j .lit4 -j .sbss -j .bss \
-O binary $elf $dat || exit 1
if [ $? == 0 -a $verbose = true ]; then
mips-objdump -z -D -EL -M reg-names=numeric --show-raw-insn \
--section .text --section .data \
--section .rodata --section .sdata --section .sbss \
--section .bss $elf
fi
if [ $? == 0 -a $miffile = true ] ; then
elf2mif.sh "$elf" || exit 1
fi
# --section .reginfo
chmod a-x $bin $dat
#!/bin/bash
# edit header files in case of change in variable definitions
# set -x
# bail out on any error
set -e
usage() {
cat << EOF
usage: $0 [options]
edits cMIPS.ld cMIPS.h cMIPS.s to keep addresses up to date
OPTIONS:
-h Show this message
-v Verbose, shows new values
EOF
}
verbose=false
while [ -n "$1" ] ; do
case "$1" in
-h) usage ; exit 1
;;
-v) verbose=true
;;
*) usage ; echo " invalid option: $1" ; exit 1
;;
esac
shift
done
if [ ! -v tree ] ; then
# you must set the location of the cMIPS root directory in the variable tree
# tree=${HOME}/cMIPS
# tree="$(dirname "$(pwd)")"
export tree="$(echo $PWD | sed -e 's:\(/.*/cMIPS\)/.*:\1:')"
fi
bin="${tree}"/bin
include="${tree}"/include
srcVHDL="${tree}"/vhdl
dfn="${srcVHDL}"/packageMemory.vhd