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Roberto Hexsel
cMIPS
Commits
b27d20fe
Commit
b27d20fe
authored
Oct 14, 2016
by
Roberto Hexsel
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core.vhd missing in CAUSE always updated -- except if STATUS.EXL=1
parent
c6c42ec6
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41 deletions
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-41
cMIPS/vhdl/core.vhd
cMIPS/vhdl/core.vhd
+27
-41
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cMIPS/vhdl/core.vhd
View file @
b27d20fe
...
...
@@ -156,7 +156,7 @@ architecture rtl of core is
signal
update
,
not_stalled
:
std_logic
;
signal
update_reg
:
reg5
;
signal
status_update
,
epc_update
,
compare_update
:
std_logic
;
signal
cause_update
,
disable_count
,
compare_set
,
compare_clr
:
std_logic
;
signal
disable_count
,
compare_set
,
compare_clr
:
std_logic
;
signal
STATUSinp
,
STATUS
,
CAUSEinp
,
CAUSE
,
EPCinp
,
EPC
:
reg32
;
signal
COUNT
,
COMPARE
:
reg32
;
signal
count_eq_compare
,
count_update
,
count_enable
:
std_logic
;
...
...
@@ -2327,11 +2327,8 @@ begin
variable
newCAUSE
:
reg32
;
begin
if
STATUS
(
STATUS_EXL
)
=
'0'
then
newCAUSE
(
CAUSE_BD
)
:
=
is_delayslot
;
-- instr is in delay slot
else
newCAUSE
(
CAUSE_BD
)
:
=
CAUSE
(
CAUSE_BD
);
-- hold it on a double fault
end
if
;
if
STATUS
(
STATUS_EXL
)
=
'0'
then
-- no exception, update CAUSE
newCAUSE
(
CAUSE_BD
)
:
=
is_delayslot
;
newCAUSE
(
CAUSE_TI
)
:
=
count_eq_compare
;
newCAUSE
(
CAUSE_CE1
)
:
=
'0'
;
newCAUSE
(
CAUSE_CE0
)
:
=
'0'
;
...
...
@@ -2352,6 +2349,9 @@ begin
newCAUSE
(
7
)
:
=
'0'
;
newCAUSE
(
6
downto
2
)
:
=
ExcCode
;
newCAUSE
(
1
downto
0
)
:
=
b"00"
;
else
newCAUSE
:
=
CAUSE
;
-- hold it on an exception
end
if
;
if
(
update
=
'1'
and
update_reg
=
cop0reg_CAUSE
)
then
CAUSEinp
<=
newCAUSE
(
CAUSE_BD
downto
CAUSE_CE0
)
&
...
...
@@ -2365,22 +2365,9 @@ begin
end
if
;
end
process
COP0_COMPUTE_CAUSE
;
COP0_CAUSE_HOLD
:
process
(
rst
,
clk
,
ExcCode
,
is_exception
,
MM_cop0_reg
,
not_stalled
)
variable
state
:
reg32
;
begin
if
rst
=
'0'
then
-- hold CAUSE until it is read
cause_update
<=
'0'
;
elsif
(
rising_edge
(
clk
)
and
(
ExcCode
/=
cop0code_NULL
)
)
then
cause_update
<=
'1'
;
-- syscall/trap/interrupt/exception
elsif
(
rising_edge
(
clk
)
and
(
is_exception
=
exMFC0
)
and
MM_cop0_reg
=
cop0reg_CAUSE
and
(
not_stalled
=
'1'
)
)
then
cause_update
<=
'0'
;
-- CAUSE is being read
end
if
;
end
process
COP0_CAUSE_HOLD
;
COP0_CAUSE
:
register32
generic
map
(
RESET_CAUSE
)
port
map
(
clk
,
rst
,
cause_update
,
CAUSEinp
,
CAUSE
);
port
map
(
clk
,
rst
,
'0'
,
CAUSEinp
,
CAUSE
);
-- EPC -- pg 97 -- cop0_14 -------------------
...
...
@@ -2418,8 +2405,7 @@ begin
COP0_COUNT_INTERRUPT
:
FFD
port
map
(
clk
,
rst
,
'1'
,
compare_set
,
count_eq_compare
);
disable_count
<=
CAUSE
(
CAUSE_DC
)
when
(
cause_update
=
'0'
and
CAUSE
(
CAUSE_DC
)
/=
count_enable
)
disable_count
<=
CAUSE
(
CAUSE_DC
)
when
(
CAUSE
(
CAUSE_DC
)
/=
count_enable
)
else
count_enable
;
-- load new CAUSE(CAUSE_DC)
COP0_DISABLE_COUNT
:
FFD
port
map
(
clk
,
'1'
,
rst
,
disable_count
,
count_enable
);
...
...
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