Commit c9400bea authored by Roberto Hexsel's avatar Roberto Hexsel

added program that turns the board into a clock

parent 1ad34d5e
......@@ -86,7 +86,7 @@ while true ; do
;;
-n) names=true
;;
-mif|-m) miffile=true
-mif | -m | -syn ) miffile=true
;;
-x) set -x
;;
......@@ -103,6 +103,14 @@ if [ -z $inp ] ; then usage ; exit 1 ; fi
pkg_vhd="${srcVHDL}"/packageMemory.vhd
if [ $miffile = true ]; then
S="-D FOR_SYNTHESIS" ;
touch $pkg_vhd -r ${srcVHDL}/packageMemory_fpga.vhd
else
S="-U FOR_SYNTHESIS" ;
touch $pkg_vhd -r ${srcVHDL}/packageMemory_simu.vhd
fi
if [ $pkg_vhd -nt $c_ld -o $pkg_vhd -nt $c_s ] ; then
"${bin}"/edMemory.sh -v || errorED || exit 1
fi
......
......@@ -84,9 +84,8 @@ while true ; do
;;
-n) names=false
;;
-mif) miffile=true
;;
-syn) synth=true
-mif | -syn ) synth=true
miffile=true
;;
-x) set -x
;;
......@@ -111,10 +110,22 @@ c_h="${include}"/cMIPS.h
c_s="${include}"/cMIPS.s
c_io="${include}"/cMIPSio
# c_start="${include}"/start ## see below for synthesis version
c_hndlrs="${include}"/handlers
# c_hndlrs="${include}"/handlers ## see below for synthesis version
pkg_vhd="${srcVHDL}"/packageMemory.vhd
if [ $synth = true ]; then
S="-D FOR_SYNTHESIS" ;
c_start="${include}"/syn_start
c_hndlrs="${include}"/syn_handlers
touch $pkg_vhd -r ${srcVHDL}/packageMemory_fpga.vhd
else
S="-U FOR_SYNTHESIS" ;
c_start="${include}"/start
c_hndlrs="${include}"/handlers
touch $pkg_vhd -r ${srcVHDL}/packageMemory_simu.vhd
fi
if [ $pkg_vhd -nt $c_h -o\
$pkg_vhd -nt $c_ld -o\
$pkg_vhd -nt $c_s ] ; then
......@@ -130,13 +141,6 @@ dat=data.bin
if [ $verbose = true ]; then memory_map="-Map ${inp}.map" ; fi
if [ $synth = true ]; then
S="-D FOR_SYNTHESIS" ;
c_start="${include}"/syn_start
else
S="-U FOR_SYNTHESIS" ;
c_start="${include}"/start
fi
(mips-gcc -O${level} $warn -DcMIPS -mno-gpopt -I"${include}" \
-S ${src} $S -o ${asm} || exit 1) && \
......
......@@ -25,6 +25,14 @@
extern void exit(int);
extern void cmips_delay(int);
extern void delay_us(int);
extern void delay_ms(int);
extern void enableInterr(void);
extern void disableInterr(void);
extern void print(int);
extern void to_stdout(char c);
extern int from_stdin(void);
......@@ -33,27 +41,22 @@ extern void writeInt(int);
extern void writeClose(void);
extern int readInt(int*);
extern void dumpRAM(void);
extern int print_sp(void);
extern void cmips_delay(int);
extern void delay_us(int);
extern void delay_ms(int);
extern char *memcpy(char*, const char*, int);
extern char *memset(char*, const int, int);
// external counter (peripheral)
extern void startCounter(int, int);
extern void stopCounter(void);
extern int readCounter(void);
extern void enableInterr(void);
extern void disableInterr(void);
// internal counter, CP0 register COUNT
extern int startCount(void);
extern int stopCount(void);
extern int readCount(void);
extern char *memcpy(char*, const char*, int);
extern char *memset(char*, const int, int);
// LCD display (Macnica board)
extern void LCDinit(void);
extern int LCDprobe(void);
extern int LCDset(int);
......@@ -63,13 +66,15 @@ extern void LCDtopLine(void);
extern void LCDbotLine(void);
extern void LCDgotoxy(int, int);
extern void LCDputc(char);
extern void LCDprint(unsigned int);
extern void DSP7SEGput(int MSD, int MSdot, int lsd, int lsdot);
// 7-segment display and keyboard (Macnica board)
extern void DSP7SEGput(int, int, int, int);
extern int KBDget(void);
extern int SWget(void);
// struct to access the system statistics "peripheral"
// struct to access the cache system statistics "peripheral"
typedef struct sStats {
int dc_ref; // data cache references
int dc_rd_hit; // data cache read-hits
......
......@@ -350,6 +350,33 @@ void LCDputc(char c) {
}
}
#define conv(c) ((c<10)?((c)+0x30):((c)+('a'-10)))
// write an integer to the display
void LCDprint(unsigned int n) {
int k;
k = (n >>28);
LCDput( conv(k) );
k = (n<< 4)>>28;
LCDput( conv(k) );
k = (n<< 8)>>28;
LCDput( conv(k) );
k = (n<<12)>>28;
LCDput( conv(k) );
k = (n<<16)>>28;
LCDput( conv(k) );
k = (n<<20)>>28;
LCDput( conv(k) );
k = (n<<24)>>28;
LCDput( conv(k) );
k = (n<<28)>>28;
LCDput( conv(k) );
}
//-----------------------------------------------------------------------
......
This diff is collapsed.
......@@ -67,7 +67,6 @@ _start: nop
# set STATUS, cop0, hw interrupt IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, 0x1000e011
mtc0 $k0, cop0_STATUS
j main
nop
......@@ -77,7 +76,7 @@ _start: nop
##
exit:
_exit: la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x0311 # display .1.1
li $k1, 0x0300 # display .0.0
sw $k1, 0($k0) # write to 7 segment display
hexit: j hexit # wait forever
......@@ -85,6 +84,15 @@ hexit: j hexit # wait forever
.end _start
##
## read contants of the stack-pointer (for debugging)
##
.global print_sp
.ent print_sp
print_sp:
jr $ra
move $v0, $sp
.end print_sp
##
##================================================================
......@@ -139,7 +147,8 @@ h0100: j h0100 # wait forever
.org x_EXCEPTION_0180,0
_excp_0180:
la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x0377 # display .7.7
mfc0 $k1, c0_cause
andi $k1, $k1, 0x07f # display .7.7
sw $k1, 0($k0) # write to 7 segment display
h0180: j h0180 # wait forever
nop
......@@ -157,17 +166,76 @@ heret: j heret # wait forever
nop
##
##===============================================================
## interrupt handlers at exception vector 0200
##
.org x_EXCEPTION_0200,0
# declare all handlers here, these must be in file syn_handlers.s
.extern countCompare # IRQ7 = hwIRQ5, Cop0 counter
.extern UARTinterr # IRQ6 - hwIRQ4, see vhdl/tb_cMIPS.vhd
.extern extCounter # IRQ5 - hwIRQ3, see vhdl/tb_cMIPS.vhd
.set M_CauseIM,0x0000e000 # keep bits 15..8 -> IM = IP
.set M_StatusIEn,0xe011 # user mode, enable all interrupts, EXL=0
.set noreorder
.org x_EXCEPTION_0200,0 # exception vector_200, interrupt handlers
.ent _excp_0200
_excp_0200:
la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x0366 # display .6.6
sw $k1, 0($k0) # write to 7 segment display
h0200: j h0200 # wait forever
nop
mfc0 $k0, c0_cause
andi $k0, $k0, M_CauseIM # Keep only IP bits from Cause
mfc0 $k1, c0_status
and $k0, $k0, $k1 # and mask with IM bits
srl $k0, $k0, 10 # keep only 3 MS bits of IP (irq7..5)
lui $k1, %hi(handlers_tbl) # plus displacement in j-table of 8 bytes
ori $k1, $k1, %lo(handlers_tbl)
add $k1, $k1, $k0
nop
jr $k1
nop
## the code for each handler must repeat the exception return
## sequence shown below in excp_0200ret.
handlers_tbl:
j dismiss # no request: 000
nop
j extCounter # lowest priority, IRQ5: 001
nop
j UARTinterr # mid priority, IRQ6: 01x
nop
j UARTinterr
nop
j countCompare # highest priority, IRQ7: 1xx
nop
j countCompare
nop
j countCompare
nop
j countCompare
nop
dismiss: # No pending request, must have been noise
# do nothing and return
_excp_0200ret:
mfc0 $k0, c0_status # Read STATUS register
ori $k0, $k0, M_StatusIEn # and re-enable interrupts
mtc0 $k0, c0_status # else keep as it was on int entry
eret # Return from interrupt
nop
.end _excp_0200
#-----------------------------------------------------------------
##
......
//
// chronometer on the LCD display
//
// external counter interrupts 4 times per second
// displays shows a tumbling star plus counter that increments every second
//
#include "cMIPS.h"
extern int _counter_val;
int conv1(int);
#define FALSE (0==1)
#define TRUE !FALSE
#define QUARTER 12500000
int main(void) {
int i, j, k;
volatile int old_val;
int sec, min, hour;
LCDinit();
LCDtopLine();
#if 1
LCDput(' ');
LCDput('H');
LCDput('e');
LCDput('l');
LCDput('l');
LCDput('o');
LCDput(' ');
LCDput('w');
LCDput('o');
LCDput('r');
LCDput('l');
LCDput('d');
LCDput('!');
#else
LCDprint( print_sp() );
#endif
LCDbotLine();
_counter_val = 0; // variable to accumulate number of interrupts
old_val = _counter_val;
enableInterr();
startCounter(QUARTER,TRUE); // counter will interrupt after N cycles
sec = min = hour = 0;
i = 0;
while (TRUE) {
while (old_val == _counter_val) {// wait for interrupt
delay_us(i);
}
old_val = _counter_val;
switch(i) {
case 0:
j = 0x09; break;
case 1:
j = 0x0b; break;
case 2:
j = 0x0c; break;
default:
j = 0xa; i = -1; sec += 1 ; break;
};
i += 1;
LCDgotoxy(1, 2);
LCDput(j);
if (sec == 60) {
min += 1;
sec = 0;
}
if (min == 60) {
hour += 1;
min = 0;
}
LCDgotoxy(4, 2);
#define conv(a) ((a<10)?((a)+0x30):((a)+('a'-10)))
k = (hour>>4) & 0x0f;
LCDput( conv(k) );
k = hour & 0x0f;
LCDput( conv(k) );
LCDput(':');
k = (min>>4) & 0x0f;
LCDput( conv(k) );
k = min & 0x0f;
LCDput( conv(k) );
LCDput(':');
k = (sec>>4) & 0x0f;
LCDput( conv(k) );
k = sec & 0x0f;
LCDput( conv(k) );
}
return 0;
}
int conv1(int c) {
int i;
switch(c) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 9:
i = c + 0x30; ; break;
case 10:
i = 'a'; break;
case 11:
i = 'b'; break;
case 12:
i = 'c'; break;
case 13:
i = 'd'; break;
case 14:
i = 'e'; break;
case 15:
i = 'f'; break;
default:
i = '*';
}
return(i);
}
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
[*] Sun May 17 23:47:43 2015
[*] Tue Mar 28 23:27:02 2017
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
[dumpfile_mtime] "Sun May 17 23:34:01 2015"
[dumpfile_size] 24210019
[dumpfile_mtime] "Tue Mar 28 23:24:11 2017"
[dumpfile_size] 24414101
[savefile] "/home/roberto/cMIPS/v_irx.sav"
[timestart] 6435000000
[size] 1200 908
[pos] 676 118
*-29.000000 7800000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 14501000000
[size] 1200 905
[pos] 676 70
*-30.000000 7800000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_simple_uart.
[sst_width] 210
[signals_width] 221
[sst_expanded] 1
[sst_vpaned_height] 266
[sst_vpaned_height] 269
@28
clk
@22
......@@ -23,8 +23,6 @@ u_core.pc[31:0]
- decode, reg fetch
@22
u_core.rf_instruction[31:0]
u_core.regs_a[31:0]
u_core.regs_b[31:0]
@200
- exec
@24
......@@ -72,7 +70,7 @@ u_simple_uart.u_uart.s_ctrl
u_simple_uart.u_uart.ctrl[7:0]
@28
u_simple_uart.u_uart.s_rx
@22
@821
u_simple_uart.u_uart.rxreg[7:0]
@28
u_simple_uart.irq
......@@ -93,5 +91,6 @@ u_simple_uart.u_uart.rxdat
u_uart_remota.tx_dbg_st[31:0]
@28
u_uart_remota.outdat
u_uart_remota.tx_clk
[pattern_trace] 1
[pattern_trace] 0
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
[*] Fri Apr 8 16:29:19 2016
[*] Tue Mar 28 23:23:27 2017
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
[dumpfile_mtime] "Fri Apr 8 13:54:30 2016"
[dumpfile_size] 11860622
[dumpfile_mtime] "Tue Mar 28 23:18:27 2017"
[dumpfile_size] 12342617
[savefile] "/home/roberto/cMIPS/v_rx.sav"
[timestart] 1652600000
[size] 1133 1018
[pos] -1 -1
*-26.000000 1820000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 0
[size] 1133 881
[pos] 40 -1
*-31.000000 2283000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
[treeopen] u_simple_uart.
[sst_width] 210
[signals_width] 218
[sst_expanded] 1
[sst_vpaned_height] 304
[sst_vpaned_height] 255
@28
clk
@22
......@@ -49,6 +49,14 @@ u_core.mm_wrmem
u_core.data_inp[31:0]
u_core.data_out[31:0]
@200
- write-back
@28
u_core.wb_muxc[2:0]
u_core.wb_wreg
@22
u_core.wb_a_c[4:0]
u_core.wb_c[31:0]
@200
- UART
@28
u_simple_uart.u_uart.rts
......@@ -64,42 +72,21 @@ u_simple_uart.u_uart.ctrl[7:0]
@24
u_simple_uart.u_uart.rxcpu_dbg_st[31:0]
u_simple_uart.u_uart.rx_dbg_st[31:0]
@29
@28
u_simple_uart.u_uart.s_rx
@22
u_simple_uart.u_uart.rxreg[7:0]
@28
u_simple_uart.u_uart.interr_rx_full
@200
- transmission circuit
@24
u_simple_uart.u_uart.txcpu_dbg_st[31:0]
u_simple_uart.u_uart.tx_dbg_st[31:0]
@22
u_simple_uart.u_uart.txreg[7:0]
@28
u_simple_uart.u_uart.txclk
u_simple_uart.u_uart.txdat
u_simple_uart.u_uart.interr_tx_empty
u_simple_uart.u_uart.sta_recv_sto[9:0]
u_simple_uart.u_uart.rxdat
@29
u_simple_uart.u_uart.rxclk
@200
- REMOTE (fake) UART
@24
u_uart_remota.tx_dbg_st[31:0]
@28
u_uart_remota.outdat
@24
u_uart_remota.rx_dbg_st[31:0]
@28
u_uart_remota.recv[7:0]
@22
u_uart_remota.recv[7:0]
@200
- write-back
@28
u_core.wb_muxc[2:0]
u_core.wb_wreg
@22
u_core.wb_a_c[4:0]
u_core.wb_c[31:0]
u_uart_remota.tx_clk
[pattern_trace] 1
[pattern_trace] 0
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
[*] Sun May 17 23:22:05 2015
[*] Tue Mar 28 23:17:37 2017
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
[dumpfile_mtime] "Sun May 17 23:20:27 2015"
[dumpfile_size] 22609843
[dumpfile_mtime] "Tue Mar 28 23:15:02 2017"
[dumpfile_size] 21988875
[savefile] "/home/roberto/cMIPS/v_tx.sav"
[timestart] 1526000000
[size] 1062 917
[pos] 676 109
*-30.000000 2000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 0
[size] 1062 876
[pos] 854 8
*-33.000000 7730600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
[treeopen] u_simple_uart.
[sst_width] 210
[signals_width] 218
[sst_expanded] 1
[sst_vpaned_height] 268
[sst_vpaned_height] 255
@28
clk
@22
......@@ -27,6 +27,7 @@ u_core.instr_fetched[31:0]
@22
u_core.regs_a[31:0]
u_core.regs_b[31:0]
u_core.rf_instruction[31:0]
@200
- exec
@24
......@@ -45,11 +46,21 @@ d_addr[31:0]
cpu_d_aval
u_core.mm_wrmem
@22
u_print_data.data[31:0]
u_core.data_inp[31:0]
u_core.data_out[31:0]
@200
- UART
- write-back
@28
u_core.wb_muxc[2:0]
u_core.wb_wreg
@22
u_core.wb_a_c[4:0]
u_core.wb_c[31:0]
@200
- UART
@29
u_simple_uart.u_uart.s_stat
@28
u_simple_uart.u_uart.status[7:0]
u_simple_uart.u_uart.s_ctrl
u_simple_uart.u_uart.ctrl[7:0]
......@@ -68,7 +79,7 @@ u_simple_uart.u_uart.tx_dbg_st[31:0]
u_simple_uart.u_uart.tx_shr_full
u_simple_uart.u_uart.txclk
u_simple_uart.u_uart.txdat
@23
@22
u_interrupt_counter.q[29:0]
@200
- REMOTE (fake) UART
......@@ -78,13 +89,5 @@ u_uart_remota.rx_dbg_st[31:0]
u_uart_remota.recv[7:0]
@22
u_uart_remota.recv[7:0]
@200
- write-back
@28
u_core.wb_muxc[2:0]
u_core.wb_wreg
@22
u_core.wb_a_c[4:0]
u_core.wb_c[31:0]
[pattern_trace] 1
[pattern_trace] 0
......@@ -1407,7 +1407,7 @@ begin
addrError <= i_addrError;
-- assert mem_excp_type = exNOP -- DEBUG
-- report "SIMULATION ERROR -- data addressing error: " &
-- report LF & "SIMULATION ERROR -- data addressing error: " &
-- integer'image(exception_type'pos(mem_excp_type)) &
-- " at address: " & SLV32HEX(v_addr)
-- severity error;
......@@ -1422,7 +1422,7 @@ begin
-- EX_addr <= v_addr; -- without TLB
-- assert ( (phy_d_addr = v_addr) and (EX_aVal = '0') ) -- DEBUG
-- report "mapping mismatch V:P "&SLV32HEX(v_addr)&":"&SLV32HEX(phy_d_addr);
-- report LF&"mapping mismatch V:P "&SLV32HEX(v_addr)&":"&SLV32HEX(phy_d_addr);
EX_wreg <= EX_wreg_pre -- movz,movn, move/DO_NOT move
......@@ -2690,11 +2690,17 @@ begin
i_stage_mm := FALSE;
i_exception := FALSE;
end if;
-- uncomment when making use of the TLB
TLB_excp_type <= i_excp_type;
tlb_stage_MM <= i_stage_mm;
tlb_exception <= i_exception and not(SL2BOOL(tlb_ex_2));
-- uncomment when NOT making use of the TLB
-- TLB_excp_type <= exNOP;
-- tlb_stage_MM <= FALSE;
-- tlb_exception <= FALSE;
end process MMU_exceptions; -- -----------------------------------------
-- catch only first exception, if there are two in consecutive cycles
......
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