Commit f0fe6e47 authored by Roberto Hexsel's avatar Roberto Hexsel

new gtkwave configuration files with min,Medium,MAX detail

parent 2aab8110
......@@ -85,7 +85,7 @@ options="--ieee-asserts=disable --stop-time=${length}${unit}s --vcd=${visual}"
if [ -v $WAVE ] ; then
## simulator must be exec'd so it can read from the standard input
exec "${simulator}" $options
exec "${simulator}" $options --vcd-nodate
else
......
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
[*] Wed Aug 17 13:40:37 2016
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
[dumpfile_mtime] "Wed Aug 17 13:34:05 2016"
[dumpfile_size] 6865336
[savefile] "/home/roberto/cMIPS/pipe_MAX.sav"
[timestart] 183000000
[size] 1201 876
[pos] 445 -1
*-26.000000 262800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
[treeopen] u_fpu.
[treeopen] u_lcd_display.
[sst_width] 210
[signals_width] 214
[sst_expanded] 1
[sst_vpaned_height] 278
@28
clk
@200
-== FETCH ======
@22
u_core.pc[31:0]
@28
u_core.pcsel[1:0]
@22
u_core.pcincd[31:0]
u_core.br_target[31:0]
u_core.j_target[31:0]
@28
u_core.br_stall
u_core.jr_stall
u_core.lw_stall
u_core.sw_stall
@200
-== DECOD =====
@22
u_core.rf_instruction[31:0]
u_core.opcode[5:0]
@24
u_core.a_rs[4:0]
u_core.a_rt[4:0]
u_core.a_rd[4:0]
u_core.a_c[4:0]
@200
-== EXEC =======
@24
u_core.u_alu.operation[31:0]
u_core.ex_a_c[4:0]
@22
u_core.alu_inp_a[31:0]
u_core.alu_inp_b[31:0]
u_core.result[31:0]
@200
-== MEM =======
@28
cpu_d_aval
wr
u_core.b_sel[3:0]
@22
d_addr[31:0]
u_core.data_inp[31:0]
u_core.data_out[31:0]
@200
-== WR BACK =====
@24
u_core.wb_muxc[2:0]
@22
u_core.wb_pc_p8[31:0]
u_core.wb_a[31:0]
u_core.wb_mem_data[31:0]
u_core.wb_cop0_val[31:0]
u_core.wb_result[31:0]
u_core.wb_hi[31:0]
u_core.wb_lo[31:0]
@29
u_core.wb_wreg
@24
u_core.wb_a_c[4:0]
@22
u_core.wb_c[31:0]
[pattern_trace] 1
[pattern_trace] 0
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
[*] Wed Aug 17 13:32:42 2016
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
[dumpfile_mtime] "Wed Aug 17 13:18:43 2016"
[dumpfile_size] 6865336
[savefile] "/home/roberto/cMIPS/pipe_Med.sav"
[timestart] 183000000
[size] 1201 960
[pos] -1 -1
*-26.000000 262800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
[treeopen] u_fpu.
[treeopen] u_lcd_display.
[sst_width] 210
[signals_width] 214
[sst_expanded] 1
[sst_vpaned_height] 309
@28
clk
@200
-== FETCH ======
@22
u_core.pc[31:0]
u_core.instr_fetched[31:0]
@28
u_core.pcsel[1:0]
@22
u_core.pcincd[31:0]
u_core.br_target[31:0]
u_core.j_target[31:0]
@200
-== DECOD ======
@22
u_core.rf_instruction[31:0]
u_core.opcode[5:0]
@24
u_core.a_rs[4:0]
u_core.a_rt[4:0]
u_core.a_rd[4:0]
u_core.a_c[4:0]
@200
-== EXEC =======
@24
u_core.u_alu.operation[31:0]
@200
-forward into A
@22
u_core.mm_result[31:0]
u_core.wb_c[31:0]
u_core.ex_a[31:0]
u_core.alu_inp_a[31:0]
@200
-forward into B
@22
u_core.mm_result[31:0]
u_core.wb_c[31:0]
u_core.ex_b[31:0]
u_core.ex_displ32[31:0]
u_core.alu_inp_b[31:0]
u_core.result[31:0]
@200
-== MEM =======
@28
cpu_d_aval
wr
u_core.b_sel[3:0]
@22
d_addr[31:0]
u_core.data_inp[31:0]
@200
-forward to mem
@22
u_core.mm_b[31:0]
u_core.wb_c[31:0]
u_core.data_out[31:0]
@200
-== WR BACK =====
@24
u_core.wb_muxc[2:0]
@22
u_core.wb_rd_data[31:0]
u_core.wb_result[31:0]
u_core.wb_hi[31:0]
u_core.wb_lo[31:0]
u_core.wb_c[31:0]
@24
u_core.wb_a_c[4:0]
@28
u_core.wb_wreg
[pattern_trace] 1
[pattern_trace] 0
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
[*] Wed Aug 17 13:11:28 2016
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
[dumpfile_mtime] "Wed Aug 17 13:06:45 2016"
[dumpfile_size] 6865336
[savefile] "/home/roberto/cMIPS/pipe_min.sav"
[timestart] 1038600000
[size] 1201 673
[pos] -1 -1
*-26.000000 262800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
[treeopen] u_fpu.
[treeopen] u_lcd_display.
[sst_width] 210
[signals_width] 214
[sst_expanded] 1
[sst_vpaned_height] 197
@28
clk
@200
- fetch
@22
u_core.pc[31:0]
@200
-
- decode, reg fetch
@22
u_core.rf_instruction[31:0]
u_core.opcode[5:0]
@24
u_core.a_rs[4:0]
u_core.a_rt[4:0]
u_core.a_rd[4:0]
u_core.a_c[4:0]
@200
-
- exec
@24
u_core.u_alu.operation[31:0]
@22
u_core.alu_inp_a[31:0]
u_core.alu_inp_b[31:0]
u_core.result[31:0]
@200
-
- memory
@28
cpu_d_aval
u_core.b_sel[3:0]
wr
@22
d_addr[31:0]
u_core.data_inp[31:0]
u_core.data_out[31:0]
@200
-
- write-back
@28
u_core.wb_wreg
@25
u_core.wb_a_c[4:0]
@22
u_core.wb_c[31:0]
[pattern_trace] 1
[pattern_trace] 0
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