Commit ff455188 authored by Roberto Hexsel's avatar Roberto Hexsel

fixed PageTable allocation in mid-ram

parent f0fe6e47
......@@ -86,6 +86,15 @@ then
fi
done
# set up address for base of Page Table
VAR=x_DATA_BASE_ADDR
NEW=$(egrep -h ${VAR} "${dfn}" | sed -n -e '/reg32/s/.*x"\(.*\)".*/\1/p')
OLD=$(egrep -h ${VAR} "${lnk}" | sed -n -e 's/.* = 0x\(.*\); .*/\1/p')
# echo -n -e "$NEW $OLD\n"
if [ -n "$OLD" ] ; then
sed -i -e '/'$VAR'/s/'$OLD'/'$NEW'/' "${lnk}"
fi
# set up address for base of Page Table
VAR=x_DATA_MEM_SZ
NEW=$(egrep -h ${VAR} "${dfn}" | sed -n -e '/reg32/s/.*x"\(.*\)".*/\1/p')
......
......@@ -77,8 +77,8 @@ gfile=${gtkwconf%%.sav}
sav="${tree}"/${gfile}.sav
"${bin}"/build.sh || exit 1
"${bin}"/build.sh || exit 1
options="--ieee-asserts=disable --stop-time=${length}${unit}s --vcd=${visual}"
......@@ -95,5 +95,5 @@ fi
# --wave=${visual%.vcd}.ghw
## --wave=${visual%.vcd}.ghw
......@@ -43,9 +43,10 @@ SECTIONS
_end = . ; /* end of image constant (from Xinu) */
} > ram
start_RAM = 0x00040000; /* x_DATA_BASE_ADDR */
end_RAM = 0x00020000; /* x_DATA_MEM_SZ */
half_RAM = (end_RAM / 2);
base_PT = ( _bdata + half_RAM );
half_RAM = (end_RAM >> 1);
base_PT = ( start_RAM + half_RAM );
.PT base_PT : { *(.PT) } > ram
}
......@@ -560,5 +560,13 @@ _kmsg_list:
.word _kmsg_interr,_kmsg_excep, _kmsg_prot_viol, _kmsg_seg_fault
.word _kmsg_sec_mem
##
## need this so the allocation of the PageTable does not break B^(
##
.section .data
.align 2
_end_of_data:
.word 0
#----------------------------------------------------------------
......@@ -117,7 +117,6 @@ _start:
sw $a1, 0($a0) # write to PT[ _PTV ].entryLo0
sw $a2, 8($a0) # write to PT[ _PTV ].entryLo1
# pin down first five TLB entries: ROM[0], I/O, RAM[0], stack, PgTbl
li $k0, 5
mtc0 $k0, c0_wired
......@@ -431,14 +430,14 @@ PT_update:
## Status: 00=unmapped, 01=mapped, 10=in_secondary_storage, 11=undef
##
.section .PT,"aw",@progbits
.align 4
.global _PT
## ( ( (x_INST_BASE_ADDR + n*4096) >>12 )<<6 ) || 0b000011 d,v,g
_PT:
##
## ROM mappings, intLo{01} = U=M=W=0, X=1, S=10 (or 00) = 6 (or 4)
##
.org (_PT + (x_INST_BASE_ADDR >>13)*16)
_PT: .org (_PT + (x_INST_BASE_ADDR >>13)*16)
# PT[0], ROM
PTbase: .word ( (x_INST_BASE_ADDR + 0*4096) >>6) | 0b000011
......
......@@ -17,9 +17,9 @@
//-----------------------------------------------------------------------
// decide on the tests to run
#define WALK_THE_PT 1
#define WALK_THE_PT 0
#define TLB_MODIFIED 1
#define DOUBLE_FAULT 1
#define DOUBLE_FAULT 0
// these will abort the simulation when the fault is detected/handled
#define PROT_VIOL 0
......@@ -69,7 +69,7 @@ void main(void) {
walker = (int *)((int)walker + 4096);
}
print_str("\twalked\n");
print_str("\n\twalked\n");
#endif
......@@ -95,9 +95,9 @@ void main(void) {
// first, remove V_addr from the TLB, to ensure the PT is searched
if ( TLB_purge((void *)walker) == 0 ) {
print_str("\n\tTLB entry purged\n");
print_str("\n\tTLB entry purged\n\n");
} else {
print_str("\n\tTLB miss\n");
print_str("\n\tTLB miss\n\n");
}
new_value = ( ((x_DATA_BASE_ADDR + PG_NUM*4096)>>12) <<6) | 0b000011; // d=0
......@@ -110,9 +110,9 @@ void main(void) {
if ( *walker == 0x99 ) { // this load is optimized away by gcc
print( *walker );
print_str("\tMod ok\n\n");
print_str("\n\tMod ok\n");
} else {
print_str("\tMod err\n\n");
print_str("\n\tMod err\n");
}
#endif
......@@ -176,9 +176,9 @@ void main(void) {
// first, remove V_addr from the TLB, to ensure the PT is searched
if ( TLB_purge((void *)walker) == 0 ) {
print_str("\n\tpurged\n");
print_str("\tpurged\n");
} else {
print_str("\t\tTLB miss\n");
print_str("\tTLB miss\n");
}
// change a PT element so it is data, NON-writable, page is mapped in PT
......@@ -214,9 +214,9 @@ void main(void) {
// first, remove V_addr from the TLB, to ensure the PT will be searched
if ( TLB_purge((void *)walker) == 0 ) {
print_str("\n\tpurged\n");
print_str("\tpurged\n");
} else {
print_str("\n\tTLB miss\n");
print_str("\tTLB miss\n");
}
// add a new PT element for an address range with RAM but UN-mapped
......
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
[*] Sun May 17 11:56:41 2015
[*] Fri Oct 14 01:02:39 2016
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
[dumpfile_mtime] "Sun May 17 11:56:25 2015"
[dumpfile_size] 2177591
[dumpfile_mtime] "Fri Oct 14 01:01:44 2016"
[dumpfile_size] 4593625
[savefile] "/home/roberto/cMIPS/tlb.sav"
[timestart] 1137200000
[size] 1213 1026
[timestart] 2062800000
[size] 1240 1018
[pos] -1 -1
*-25.727983 1188300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-25.727983 2022300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
[sst_width] 210
[signals_width] 213
[sst_width] 221
[signals_width] 208
[sst_expanded] 1
[sst_vpaned_height] 331
@28
......@@ -25,24 +25,15 @@ u_core.instr_fetched[31:0]
@28
u_core.pcsel[1:0]
u_core.excp_pcsel[2:0]
u_core.exception_stall
u_core.nullify
u_core.abort
u_core.annul_twice
@200
- decode, reg fetch
@22
u_core.rf_instruction[31:0]
@24
u_core.a_rs[4:0]
u_core.a_rt[4:0]
u_core.a_rd[4:0]
u_core.exception_dec[31:0]
@200
- exec
@28
u_core.ex_wreg
@24
u_core.u_alu.operation[31:0]
@22
u_core.alu_inp_a[31:0]
u_core.alu_inp_b[31:0]
......@@ -51,7 +42,6 @@ u_core.v_addr[31:0]
@200
- memory
@28
u_core.mm_aval
u_core.b_sel[3:0]
@22
u_core.data_inp[31:0]
......@@ -61,66 +51,70 @@ d_addr[31:0]
cpu_d_aval
wr
@200
- write-back
@28
u_core.wb_wreg
@24
u_core.wb_a_c[4:0]
@22
u_core.wb_c[31:0]
@28
u_core.wb_muxc[2:0]
@22
u_core.wb_cop0_val[31:0]
@200
- COP-0
@28
u_core.tlb_exception
@24
u_core.exccode[4:0]
u_core.exception_num[31:0]
@22
u_core.cause[31:0]
u_core.status[31:0]
u_core.epc[31:0]
@29
u_core.is_delayslot
@22
u_core.badvaddr[31:0]
u_core.context[31:0]
@200
-
@28
u_core.tlb_exception
@24
u_core.tlb_excp_num[31:0]
u_core.mm_tlb_exception
u_core.mm_tlb_stage_mm
@200
-
@22
u_core.tlb_entryhi[31:0]
u_core.tlb_excp_va[31:13]
@28
u_core.tlb_read
@22
u_core.entryhi_inp[31:0]
@28
u_core.entryhi_update
@22
u_core.tlb_entryhi[31:0]
u_core.index[31:0]
u_core.entryhi[31:0]
u_core.tlb_entrylo0[31:0]
u_core.tlb_dat0_inp[25:0]
u_core.entrylo0[31:0]
u_core.tlb_entrylo1[31:0]
u_core.tlb_dat1_inp[25:0]
u_core.entrylo1[31:0]
@200
-
@22
u_core.index[31:0]
@24
u_core.tlb_adr[31:0]
u_core.wired[31:0]
u_core.random[31:0]
@28
u_core.hit_mm_d
u_core.hit_mm_v
u_core.hit_mm
@24
u_core.hit_mm_adr[31:0]
@28
u_core.tlb_miss
@22
u_core.tlb_tag0[31:0]
u_core.tlb_dat0_0[25:0]
u_core.tlb_dat0_1[25:0]
u_core.tlb_tag1[31:0]
u_core.tlb_dat1_0[25:0]
u_core.tlb_dat1_1[25:0]
u_core.tlb_tag2[31:0]
u_core.tlb_dat2_0[25:0]
u_core.tlb_dat2_1[25:0]
u_core.tlb_tag3[31:0]
u_core.tlb_dat3_0[25:0]
u_core.tlb_dat3_1[25:0]
u_core.tlb_tag4[31:0]
u_core.tlb_dat4_0[25:0]
u_core.tlb_dat4_1[25:0]
u_core.tlb_tag5[31:0]
u_core.tlb_dat5_0[25:0]
u_core.tlb_dat5_1[25:0]
u_core.tlb_tag6[31:0]
u_core.tlb_dat6_0[25:0]
u_core.tlb_dat6_1[25:0]
......@@ -131,17 +125,5 @@ u_core.tlb_dat7_1[25:0]
u_core.hit_pc
@24
u_core.hit_pc_adr[31:0]
@200
- write-back
@28
u_core.wb_wreg
@24
u_core.wb_a_c[4:0]
@22
u_core.wb_cop0_val[31:0]
@28
u_core.wb_muxc[2:0]
@22
u_core.wb_c[31:0]
[pattern_trace] 1
[pattern_trace] 0
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